diff --git a/src/mainboard/siemens/mc_rpl/Kconfig b/src/mainboard/siemens/mc_rpl/Kconfig index b1f7262681..4c04775b09 100644 --- a/src/mainboard/siemens/mc_rpl/Kconfig +++ b/src/mainboard/siemens/mc_rpl/Kconfig @@ -16,52 +16,26 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS - select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_CSE_LITE_SKU config BOARD_SIEMENS_MC_RPL1 select BOARD_SIEMENS_BASEBOARD_MC_RPL select DRIVERS_UART_8250IO select GEN3_EXTERNAL_CLOCK_BUFFER - select MAINBOARD_USES_IFD_EC_REGION select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_RAPTORLAKE if BOARD_SIEMENS_BASEBOARD_MC_RPL -config SOC_INTEL_CSE_LITE_SKU - bool "Use CSE Lite firmware" - default y if MC_RPL_CHROME_EC - help - Enable if CSE Lite firmware is used in your build. It is commonly - used in Chrome boards (chromebooks, chromeboxes, ...). - But since ADL RVP build can be used with or without CSE Lite firmware - it is a configurable option. Alderlake RVP boards usually don't use - an CSE Lite firmware, but are still very likely to use it in case - ChromeEC is used. - -config CHROMEOS - select GBB_FLAG_FORCE_DEV_SWITCH_ON - select GBB_FLAG_FORCE_DEV_BOOT_USB - select GBB_FLAG_FORCE_DEV_BOOT_ALTFW - select GBB_FLAG_FORCE_MANUAL_RECOVERY - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select HAS_RECOVERY_MRC_CACHE - config MAINBOARD_DIR default "siemens/mc_rpl" config VARIANT_DIR default "mc_rpl1" if BOARD_SIEMENS_MC_RPL1 -config GBB_HWID - string - depends on CHROMEOS - default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC - default "ADLRVPP TEST 2418" - config MAINBOARD_PART_NUMBER default "MC RPL1" if BOARD_SIEMENS_MC_RPL1 @@ -82,32 +56,6 @@ config OVERRIDE_DEVICETREE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_rpl.fmd" -choice - prompt "ON BOARD EC" - default MC_RPL_CHROME_EC if BOARD_SIEMENS_MC_RPL1 - help - This option allows you to select the on board EC to use. - Select whether the board has Intel EC or Chrome EC - -config MC_RPL_CHROME_EC - bool "Chrome EC" - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_BOARDID - select EC_ACPI - select EC_GOOGLE_CHROMEEC_LPC - -config MC_RPL_INTEL_EC - bool "Intel EC" - select EC_ACPI -endchoice - -config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC - select EC_GOOGLE_CHROMEEC_SWITCHES if MC_RPL_CHROME_EC - select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC - config UART_FOR_CONSOLE int default 0 @@ -118,10 +66,6 @@ config DRIVER_TPM_SPI_BUS config USE_PM_ACPI_TIMER default n if BOARD_SIEMENS_MC_RPL1 -config TPM_TIS_ACPI_INTERRUPT - int - default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3) - config GEN3_EXTERNAL_CLOCK_BUFFER bool depends on SOC_INTEL_ALDERLAKE_PCH_P diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk index b63953c0e0..00f7ea73e3 100644 --- a/src/mainboard/siemens/mc_rpl/Makefile.mk +++ b/src/mainboard/siemens/mc_rpl/Makefile.mk @@ -3,7 +3,6 @@ subdirs-y += spd bootblock-y += bootblock.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) bootblock-y += early_gpio_n.c ramstage-y += gpio_n.c @@ -12,9 +11,6 @@ bootblock-y += early_gpio.c ramstage-y += gpio.c endif -verstage-$(CONFIG_CHROMEOS) += chromeos.c - -romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c romstage-y += memory.c @@ -22,8 +18,6 @@ ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y) romstage-y += memory_rpl.c endif -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/siemens/mc_rpl/board_id.c b/src/mainboard/siemens/mc_rpl/board_id.c index 02445f2f3a..ba154243a9 100644 --- a/src/mainboard/siemens/mc_rpl/board_id.c +++ b/src/mainboard/siemens/mc_rpl/board_id.c @@ -1,15 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include #include "board_id.h" -/* Get Board ID via EC I/O port write/read */ +/* Get Board ID */ int get_board_id(void) { - static int id = 1; - - return (id & BOARD_ID_MASK); + return 1; } diff --git a/src/mainboard/siemens/mc_rpl/board_id.h b/src/mainboard/siemens/mc_rpl/board_id.h index 2988127e9b..1408573b1b 100644 --- a/src/mainboard/siemens/mc_rpl/board_id.h +++ b/src/mainboard/siemens/mc_rpl/board_id.h @@ -3,11 +3,6 @@ #ifndef _MAINBOARD_COMMON_BOARD_ID_H_ #define _MAINBOARD_COMMON_BOARD_ID_H_ -/* Board/FAB ID Command */ -#define EC_FAB_ID_CMD 0x0d -/* Bit 5:0 for Board ID */ -#define BOARD_ID_MASK 0x3f - /* * Returns board information (board id[15:8] and * Fab info[7:0]) on success and < 0 on error diff --git a/src/mainboard/siemens/mc_rpl/chromeos.c b/src/mainboard/siemens/mc_rpl/chromeos.c deleted file mode 100644 index 4c2d1e516f..0000000000 --- a/src/mainboard/siemens/mc_rpl/chromeos.c +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, - }; - if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) || - CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)) - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); - else - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1); -} - -#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) -int get_lid_switch(void) -{ - /* Lid always open */ - return 1; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} -#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ - -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - -#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||\ - CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)) -int get_ec_is_trusted(void) -{ - /* EC is trusted if not in RW. */ - return !gpio_get(GPIO_EC_IN_RW); -} -#endif diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb index 031b2f059b..9bd0d15cbd 100644 --- a/src/mainboard/siemens/mc_rpl/devicetree.cb +++ b/src/mainboard/siemens/mc_rpl/devicetree.cb @@ -41,12 +41,6 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - # Enable PCH PCIE RP 5 using CLK 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 2, diff --git a/src/mainboard/siemens/mc_rpl/ec.c b/src/mainboard/siemens/mc_rpl/ec.c deleted file mode 100644 index 14760017ef..0000000000 --- a/src/mainboard/siemens/mc_rpl/ec.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -void mainboard_ec_init(void) -{ - const struct google_chromeec_event_info info = { - .log_events = MAINBOARD_EC_LOG_EVENTS, - .sci_events = MAINBOARD_EC_SCI_EVENTS, - .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, - .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, - .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, - }; - - google_chromeec_events_init(&info, acpi_is_wakeup_s3()); -}