From 8e3bb34d4ae37feae89b4a39850b2988a334d023 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Thu, 23 Jan 2014 18:58:41 +0800 Subject: [PATCH] tegra124: Never touch MEM(MC)/EMC clocks in ramstage. The clocks for MEM(MC)/EMC should be either initialized by BootROM, or in the step of SDRAM initialization. Changing their states in ramstage may cause unexpected results (note MC even always ignores RESET states). To make it clear, we should remove MEM/EMC from the clock initialization list. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan # boots successfully. Change-Id: Icff9f78810ed5bd693b48d7b6d436ce2db919a5e Reviewed-on: https://chromium-review.googlesource.com/183623 Reviewed-by: Hung-Te Lin Commit-Queue: Hung-Te Lin Tested-by: Hung-Te Lin --- src/mainboard/google/nyan/mainboard.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 56a34031f7..6fa8a95bba 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -243,14 +243,17 @@ static void mainboard_init(device_t dev) * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out * of reset and clock-enabled, otherwise reading AHUB devices (In our * case, I2S/APBIF/AUDIO) will hang. + * + * Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either + * initialized by BootROM, or in romstage SDRAM initialization. */ clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 | CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 | CLK_L_HOST1X, - CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 | - CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, + CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC | + CLK_H_USB3, CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,