soc/intel: Refactor ITSS macros

This patch refactors ITSS related SoC specific macros by consolidating
them into a common itss.h file. This improves code maintainability and
reduces redundancy as each SoC previously defined the same macros.

Specific changes include:

- Move SoC specific ITSS macros into intelblocks/itss.h.
- SoC code now includes intelblocks/itss.h instead of the SoC-local
  soc/itss.h.
- Drop soc/itss.h from static ASL files.
- Delete soc/itss.h from all SoC locals except Apollo Lake and
  Sky Lake.

TEST=Able to build and boot google/hatch, google/xol and google/karis.

Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84183
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>

src/soc/intel/alderlake/acpi/southbridge.asl

@@ -2,7 +2,6 @@
 
 #include <intelblocks/itss.h>
 #include <intelblocks/pcr.h>
-#include <soc/itss.h>
 #include <soc/pcr_ids.h>
 
 /* PCR access */

src/soc/intel/alderlake/chip.c

@@ -15,7 +15,6 @@
 #include <intelblocks/xdci.h>
 #include <soc/hsphy.h>
 #include <soc/intel/common/vbt.h>
-#include <soc/itss.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>

src/soc/intel/alderlake/include/soc/itss.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_ADL_ITSS_H
-#define SOC_INTEL_ADL_ITSS_H
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
-#endif	/* SOC_INTEL_ADL_ITSS_H */

src/soc/intel/apollolake/include/soc/itss.h

@@ -3,11 +3,9 @@
 #ifndef _SOC_APOLLOLAKE_ITSS_H_
 #define _SOC_APOLLOLAKE_ITSS_H_
 
+#include <intelblocks/itss.h>
+
 #define GPIO_IRQ_START	50
 #define GPIO_IRQ_END	ITSS_MAX_IRQ
 
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
 #endif /* _SOC_APOLLOLAKE_ITSS_H_ */

src/soc/intel/cannonlake/include/soc/itss.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_CNL_ITSS_H
-#define SOC_INTEL_CNL_ITSS_H
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
-#endif	/* SOC_INTEL_CNL_ITSS_H */

src/soc/intel/common/block/include/intelblocks/itss.h

@@ -3,6 +3,10 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H
 #define SOC_INTEL_COMMON_BLOCK_ITSS_H
 
+#define ITSS_MAX_IRQ	119
+#define IRQS_PER_IPC	32
+#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
+
 /* PIRQA Routing Control Register */
 #define PCR_ITSS_PIRQA_ROUT	0x3100
 /* PIRQB Routing Control Register */

src/soc/intel/common/block/itss/itss.c

@@ -5,7 +5,6 @@
 #include <console/console.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/pcr.h>
-#include <soc/itss.h>
 #include <soc/pcr_ids.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 

src/soc/intel/elkhartlake/acpi/southbridge.asl

@@ -2,7 +2,6 @@
 
 #include <intelblocks/itss.h>
 #include <intelblocks/pcr.h>
-#include <soc/itss.h>
 #include <soc/pcr_ids.h>
 
 /* PCI IRQ assignment */

src/soc/intel/elkhartlake/chip.c

@@ -12,7 +12,6 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
-#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
 #include <soc/ramstage.h>

src/soc/intel/elkhartlake/include/soc/itss.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_EHL_ITSS_H
-#define SOC_INTEL_EHL_ITSS_H
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
-#endif	/* SOC_INTEL_EHL_ITSS_H */

src/soc/intel/jasperlake/acpi/southbridge.asl

@@ -2,7 +2,6 @@
 
 #include <intelblocks/itss.h>
 #include <intelblocks/pcr.h>
-#include <soc/itss.h>
 #include <soc/pcr_ids.h>
 
 /* PCI IRQ assignment */

src/soc/intel/jasperlake/chip.c

@@ -12,7 +12,6 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
-#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
 #include <soc/ramstage.h>

src/soc/intel/jasperlake/include/soc/itss.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_JSL_ITSS_H
-#define SOC_INTEL_JSL_ITSS_H
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
-#endif	/* SOC_INTEL_JSL_ITSS_H */

src/soc/intel/meteorlake/acpi/southbridge.asl

@@ -2,7 +2,6 @@
 
 #include <intelblocks/itss.h>
 #include <intelblocks/pcr.h>
-#include <soc/itss.h>
 #include <soc/pcr_ids.h>
 
 /* SoC PCR access */

src/soc/intel/meteorlake/chip.c

@@ -18,7 +18,6 @@
 #include <soc/intel/common/reset.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/iomap.h>
-#include <soc/itss.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>

src/soc/intel/meteorlake/include/soc/itss.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_MTL_ITSS_H
-#define SOC_INTEL_MTL_ITSS_H
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
-#endif	/* SOC_INTEL_MTL_ITSS_H */

src/soc/intel/skylake/acpi/pch.asl

@@ -4,7 +4,6 @@
 #include <intelblocks/pcr.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
-#include <soc/itss.h>
 #include <soc/gpe.h>
 #include <soc/pcr_ids.h>
 

src/soc/intel/skylake/chip.c

@@ -22,8 +22,8 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/interrupt.h>
 #include <soc/iomap.h>
-#include <soc/irq.h>
 #include <soc/itss.h>
+#include <soc/irq.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>

src/soc/intel/skylake/include/soc/itss.h

@@ -3,11 +3,9 @@
 #ifndef SOC_INTEL_SKL_ITSS_H
 #define SOC_INTEL_SKL_ITSS_H
 
+#include <intelblocks/itss.h>
+
 #define GPIO_IRQ_START	50
 #define GPIO_IRQ_END	ITSS_MAX_IRQ
 
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
 #endif	/* SOC_INTEL_SKL_ITSS_H */

src/soc/intel/tigerlake/acpi/southbridge.asl

@@ -2,7 +2,6 @@
 
 #include <intelblocks/itss.h>
 #include <intelblocks/pcr.h>
-#include <soc/itss.h>
 #include <soc/pcr_ids.h>
 
 /* PCR access */

src/soc/intel/tigerlake/chip.c

@@ -13,7 +13,6 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
-#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>

src/soc/intel/tigerlake/include/soc/itss.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_TGL_ITSS_H
-#define SOC_INTEL_TGL_ITSS_H
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
-#endif	/* SOC_INTEL_TGL_ITSS_H */

src/soc/intel/xeon_sp/gnr/soc_acpi.c

@@ -11,7 +11,6 @@
 #include <soc/numa.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
-#include <soc/itss.h>
 #include <soc/pcr_ids.h>
 
 int soc_madt_sci_irq_polarity(int sci)

src/soc/intel/xeon_sp/include/soc/itss.h

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_XEON_SP_ITSS_H
-#define SOC_INTEL_XEON_SP_ITSS_H
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
-
-#endif	/* SOC_INTEL_XEON_SP_ITSS_H */