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mb/google/brox/jubilant: Tune I2C timing

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Tune I2C2 timing:
Set falling time to 250ns from 400ns to meet spec: "THIGH>0.6us"

BUG=b:362685374
TEST= Build jubilant firmware
      Measure the i2c signal on jubilant to meet spec:
      I2C2 THIGH from 0.494 us to 0.76 us

Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84143
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Ren Kuo 2024-08-30 19:12:19 +08:00 • committed by Karthik Ramasubramanian
commit 13cee3c195
1 changed files with 39 additions and 0 deletions
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39
src/mainboard/google/brox/variants/jubilant/overridetree.cb
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@ -37,6 +37,45 @@ chip soc/intel/alderlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type A port A0(DCI)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Trackpad |
#| I2C1 | Touchscreen |
#| I2C2 | Audio codec & Sar sensor |
#| I2C4 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 330,
.data_hold_time_ns = 50,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 350,
.data_hold_time_ns = 50,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 250,
.data_hold_time_ns = 50,
},
.i2c[4] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf