From 8bc41fc937ef36c8d652e2ec9654edeab9c1c156 Mon Sep 17 00:00:00 2001 From: Kun Liu Date: Tue, 30 Sep 2025 15:24:21 +0800 Subject: [PATCH] mb/google/trulo/var/pujjocento: Update DTT settings for thermal control The DPTF parameters were defined by the thermal team. Based on thermal table in b:448253910 comment#1 BUG=b:448253910 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I91ad12bdb58432b3c2b867278ec5b396553ac2b9 Signed-off-by: Kun Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/89380 Reviewed-by: Subrata Banik Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- .../google/brya/variants/pujjocento/overridetree.cb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb index a648520a43..8b7382c8a0 100644 --- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -215,8 +215,10 @@ chip soc/intel/alderlake register "controls.charger_perf" = "{ [0] = { 255, 4700 }, [1] = { 40, 2500 }, - [2] = { 16, 1000 }, - [3] = { 8, 500 } + [2] = { 32, 2000 }, + [3] = { 24, 1500 }, + [4] = { 16, 1000 }, + [5] = { 8, 500 } }" device generic 0 on