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soc/amd/common/block/pci/amd_pci_mmconf.c: Support 64bit ECAM MMCONF

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More complex systems, such as servers, may have scarse space below 4G
for MMIO. With multiple root bridges needing some 32bit MMIO space it
becomes very hard to squeeze all resources. Allow to set 64bit ECAM
MMCONF base address in the MSR to free some space in the 32bit address
space. Of course using 64bit ECAM MMCONF requires the use of x86_64
mode and a proper amount of address space to be mapped with page
tables.

TEST=Set ECAM MMCONF to 0x3ffb00000000 on Gigabyte MZ33-AR1 and observe
the PCI access works in the console output.

Change-Id: I80e5a1bed33e12aa089355df64cc29887acc27f2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89112
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2025-09-09 10:14:11 +02:00
commit 8b97968e53
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/common/block/pci/amd_pci_mmconf.c
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@ -10,8 +10,8 @@ void enable_pci_mmconf(void)
{
msr_t mmconf;
mmconf.hi = 0;
mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
mmconf.hi = (uint64_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS >> 32;
mmconf.lo = (CONFIG_ECAM_MMCONF_BASE_ADDRESS & 0xfff00000) | MMIO_RANGE_EN
| __fls(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
wrmsr(MMIO_CONF_BASE, mmconf);
}