From 8b97968e53d4b0ba6ecbe10dcc0890218de888e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 9 Sep 2025 10:14:11 +0200 Subject: [PATCH] soc/amd/common/block/pci/amd_pci_mmconf.c: Support 64bit ECAM MMCONF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit More complex systems, such as servers, may have scarse space below 4G for MMIO. With multiple root bridges needing some 32bit MMIO space it becomes very hard to squeeze all resources. Allow to set 64bit ECAM MMCONF base address in the MSR to free some space in the 32bit address space. Of course using 64bit ECAM MMCONF requires the use of x86_64 mode and a proper amount of address space to be mapped with page tables. TEST=Set ECAM MMCONF to 0x3ffb00000000 on Gigabyte MZ33-AR1 and observe the PCI access works in the console output. Change-Id: I80e5a1bed33e12aa089355df64cc29887acc27f2 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/89112 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/pci/amd_pci_mmconf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c index e02bcde248..e436c112f6 100644 --- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -10,8 +10,8 @@ void enable_pci_mmconf(void) { msr_t mmconf; - mmconf.hi = 0; - mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + mmconf.hi = (uint64_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS >> 32; + mmconf.lo = (CONFIG_ECAM_MMCONF_BASE_ADDRESS & 0xfff00000) | MMIO_RANGE_EN | __fls(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; wrmsr(MMIO_CONF_BASE, mmconf); }