From 8b69dcccb2f93a974e80dad82220d802a11c6d42 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 28 Feb 2026 00:15:31 +0100
Subject: [PATCH] sb/intel/lynxpoint/pcie.c: Add additional disable steps

Taken from Wildcat Point and checked against version 1.9.1 of PCH
reference code. Note down a few TODOs to be done after Lynx Point
and Wildcat Point code has been unified.

Change-Id: I91aa3f0a5ea67bd43a625f37527c9d41c277b990
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91466
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/southbridge/intel/lynxpoint/pcie.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 7aff60895c..19a1bcf203 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pciexp.h>
@@ -326,6 +327,26 @@ static void root_port_commit_config(void)
 		pci_and_config16(dev, PCI_COMMAND,
 				~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
 
+		/* 8.2 Configuration of PCI Express Root Ports */
+		/* TODO: This should not be done if a card is detected */
+		pci_or_config32(dev, 0x338, 1 << 26);
+
+		/* TODO: BWG specifies 50 ms timeout */
+		int n = 0;
+		do {
+			u32 reg32 = pci_read_config32(dev, 0x328);
+			n++;
+			if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
+				break;
+			udelay(100);
+		} while (1);
+
+		if (n > 50)
+			printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
+				dev_path(dev));
+
+		pci_or_config32(dev, 0x408, 1 << 27);
+
 		/* Disable this device if possible */
 		pch_disable_devfn(dev);
 	}