From 8b55ee05dc957bfb5b2a1122c9093059cb9115b3 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Tue, 1 Apr 2025 16:24:27 +0530 Subject: [PATCH] mb/google/brya/var/anahera: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on anahera device and verify that the device suspends to S0ix. Change-Id: I43a1277efabf8b1ca265e9aca65878da60275b38 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/87057 Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Jayvik Desai --- .../google/brya/variants/anahera/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 2670e11a8e..12566087db 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -227,6 +227,15 @@ chip soc/intel/alderlake device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end #PCIE9-12 SSD device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682""