From 89c7a5b766ac08663e38a39cbbd5074ac7092494 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Thu, 6 Mar 2025 13:48:52 +0000 Subject: [PATCH] mb/starlabs/*: Correct comments/use defs for sleep assertion Correct the comments, and use the definations where available for the sleep assertion values Change-Id: Idfd382a166c8101b5d9a79bd18c40d6763c05e7b Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/86753 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- .../starlabs/byte_adl/variants/mk_ii/devicetree.cb | 8 ++++---- .../starlabs/starbook/variants/adl/devicetree.cb | 8 ++++---- .../starlabs/starbook/variants/adl_n/devicetree.cb | 8 ++++---- .../starlabs/starbook/variants/cml/devicetree.cb | 8 ++++---- .../starlabs/starbook/variants/kbl/devicetree.cb | 8 ++++---- .../starlabs/starbook/variants/rpl/devicetree.cb | 8 ++++---- .../starlabs/starbook/variants/tgl/devicetree.cb | 8 ++++---- .../starlabs/starfighter/variants/rpl/devicetree.cb | 8 ++++---- .../starlabs/starlite_adl/variants/mk_v/devicetree.cb | 8 ++++---- 9 files changed, 36 insertions(+), 36 deletions(-) diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index df79411fa2..192c8cb216 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -11,10 +11,10 @@ chip soc/intel/alderlake }" # Power - register "pch_slp_s3_min_assertion_width" = "2" # 50ms - register "pch_slp_s4_min_assertion_width" = "3" # 1s - register "pch_slp_sus_min_assertion_width" = "3" # 500ms - register "pch_slp_a_min_assertion_width" = "3" # 2s + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" device domain 0 on device ref igpu on diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index ccbad90b06..d1e866e1bf 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -20,10 +20,10 @@ chip soc/intel/alderlake }" # Power - register "pch_slp_s3_min_assertion_width" = "2" # 50ms - register "pch_slp_s4_min_assertion_width" = "3" # 1s - register "pch_slp_sus_min_assertion_width" = "3" # 500ms - register "pch_slp_a_min_assertion_width" = "3" # 2s + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" # Device Tree device domain 0 on diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb index 5f19e50113..0e19d3df12 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb @@ -21,10 +21,10 @@ chip soc/intel/alderlake }" # Power - register "pch_slp_s3_min_assertion_width" = "2" # 50ms - register "pch_slp_s4_min_assertion_width" = "3" # 1s - register "pch_slp_sus_min_assertion_width" = "3" # 500ms - register "pch_slp_a_min_assertion_width" = "3" # 2s + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" # Device Tree device domain 0 on diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index f0398c7d97..d502b2ad53 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -29,10 +29,10 @@ chip soc/intel/cannonlake }" # Power - register "PchPmSlpS3MinAssert" = "2" # 50ms - register "PchPmSlpS4MinAssert" = "3" # 1s - register "PchPmSlpSusMinAssert" = "3" # 500ms - register "PchPmSlpAMinAssert" = "3" # 2s + register "PchPmSlpS3MinAssert" = "2" # 1ms + register "PchPmSlpS4MinAssert" = "3" # 3s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms # PCIe Clock register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 3ab819ed56..dd53a01524 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -27,10 +27,10 @@ chip soc/intel/skylake }" # Power - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "3" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmConfigSlpS3MinAssert" = "2" # 1ms + register "PmConfigSlpS4MinAssert" = "3" # 3s + register "PmConfigSlpSusMinAssert" = "3" # 1s + register "PmConfigSlpAMinAssert" = "3" # 98ms # Enable the correct decode ranges on the LPC bus. register "lpc_ioe" = "LPC_IOE_EC_4E_4F | diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 52e0411406..30c5dfc4b5 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -22,10 +22,10 @@ chip soc/intel/alderlake }" # Power - register "pch_slp_s3_min_assertion_width" = "2" # 50ms - register "pch_slp_s4_min_assertion_width" = "3" # 1s - register "pch_slp_sus_min_assertion_width" = "3" # 500ms - register "pch_slp_a_min_assertion_width" = "3" # 2s + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" # Device Tree device domain 0 on diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 7a7c386996..69a9c1af33 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -34,10 +34,10 @@ chip soc/intel/tigerlake }" # Power - register "PchPmSlpS3MinAssert" = "2" # 50ms - register "PchPmSlpS4MinAssert" = "3" # 1s - register "PchPmSlpSusMinAssert" = "3" # 500ms - register "PchPmSlpAMinAssert" = "3" # 2s + register "PchPmSlpS3MinAssert" = "2" # 1ms + register "PchPmSlpS4MinAssert" = "3" # 3s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms # Enable the correct decode ranges on the LPC bus. register "lpc_ioe" = "LPC_IOE_EC_4E_4F | diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index c37ff7271f..5c85da4a16 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -22,10 +22,10 @@ chip soc/intel/alderlake }" # Power - register "pch_slp_s3_min_assertion_width" = "2" # 50ms - register "pch_slp_s4_min_assertion_width" = "3" # 1s - register "pch_slp_sus_min_assertion_width" = "3" # 500ms - register "pch_slp_a_min_assertion_width" = "3" # 2s + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" device domain 0 on device ref igpu on diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 247c5bcaa7..38fe6d07a4 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -25,10 +25,10 @@ chip soc/intel/alderlake }" # Power - register "pch_slp_s3_min_assertion_width" = "2" # 50ms - register "pch_slp_s4_min_assertion_width" = "3" # 1s - register "pch_slp_sus_min_assertion_width" = "3" # 500ms - register "pch_slp_a_min_assertion_width" = "3" # 2s + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" # PM Util register "pmc_gpe0_dw0" = "PMC_GPP_F"