From 88eea9da6d71c28f6a6ee8a3876367c0f5acf426 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 9 Sep 2025 10:35:48 +0200 Subject: [PATCH] vendorcode/amd/opensil/turin_poc: Pass microcode pointer to OpenSIL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the new API to pass the microcode update pointer to the OpenSIL so that OpenSIL can update microcode on all cores/threads during CCX initialization. TEST=See microcode is updated on BSP in OpenSIL on Gigabyte MZ33-AR1. Change-Id: Ic35784583a1494ea162dc4a0d2fea8c9c3e1ef5f Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/89109 Tested-by: build bot (Jenkins) Reviewed-by: Alicja Michalska --- src/vendorcode/amd/opensil/turin_poc/ramstage.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/vendorcode/amd/opensil/turin_poc/ramstage.c b/src/vendorcode/amd/opensil/turin_poc/ramstage.c index f206ef5f58..27bc22e539 100644 --- a/src/vendorcode/amd/opensil/turin_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/turin_poc/ramstage.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -293,6 +294,8 @@ static void configure_sdxi(void) static void configure_ccx(void) { CCXCLASS_DATA_BLK *ccx_data = SilFindStructure(SilId_CcxClass, 0); + UCODEPATCH_BIOSENTRYINFO *ucode_info; + void *ucode; if (CONFIG(XAPIC_ONLY) || CONFIG(X2APIC_LATE_WORKAROUND)) ccx_data->CcxInputBlock.AmdApicMode = xApicMode; @@ -305,6 +308,15 @@ static void configure_ccx(void) ccx_data->CcxInputBlock.EnableSvmX2AVIC = 1; ccx_data->CcxInputBlock.EnableSvmAVIC = true; ccx_data->CcxInputBlock.AmdCStateIoBaseAddress = ACPI_CSTATE_CONTROL; + + ucode = amd_microcode_find(); + if (!ucode) { + printk(BIOS_ERR, "OpenSIL: CPU microcode not found\n"); + return; + } + + ucode_info = &ccx_data->CcxInputBlock.UcodePatchEntryInfo; + ucode_info->UcodePatchEntryAddress = (uint64_t)ucode; } void setup_opensil(void)