From 8455d95442ee9a39ecb182abf319469dde06d324 Mon Sep 17 00:00:00 2001 From: Kenji Chen Date: Sat, 20 Sep 2014 01:39:20 +0800 Subject: [PATCH] Samus: Synchronization with FRC to enable PCIe Relaxed Order. BUG=None TEST=Modify settings, build and update the image to Samus and check the settings are applied to Registers. Signed-off-by: Kenji Chen Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f Reviewed-on: https://chromium-review.googlesource.com/219073 Reviewed-by: Duncan Laurie --- src/soc/intel/broadwell/lpc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index eda528e0ba..7f54a1dcb2 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -204,6 +204,9 @@ static const struct reg_script pch_misc_init_script[] = { /* Clear status bits to prevent unexpected wake */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), + /* Enable PCIe Releaxed Order */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), #if !CONFIG_SERIRQ_CONTINUOUS_MODE