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exynos5420: Change some clock settings.

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This change adjusts some clock settings so that they match U-Boot. There are
three different changes.

1. Change the source for psgen from the oscillator clock to the pclk.
2. Change the pll feeding the SPI busses from epll to mpll, as suggested in
   the manual.
3. Change the SPI prescaller.

BUG=chrome-os-partner:19420
TEST=Built and booted into depthcharge on pit.
BRANCH=None

Change-Id: I2896c099a91bdb78bfac03fbb804ef65c3233cd0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59730
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-06-22 20:05:37 -07:00 • committed by ChromeBot
commit 82178acc91
1 changed files with 8 additions and 7 deletions
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15
src/cpu/samsung/exynos5420/setup.h
View file

@ -227,7 +227,7 @@ struct exynos5_phy_control;
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x11111111
#define CLK_SRC_TOP4_VAL 0x11110111
#define CLK_SRC_TOP5_VAL 0x11111100
#define CLK_SRC_TOP5_VAL 0x11111110
#define CLK_SRC_TOP7_VAL 0x00022200
/* CLK_DIV_TOP */
@ -332,10 +332,11 @@ struct exynos5_phy_control;
| (UART0_SEL << 4))
/* CLK_SRC_PERIC1 */
/* SRC_CLOCK = SCLK_MPLL */
#define SPI0_SEL 3
#define SPI1_SEL 3
#define SPI2_SEL 3
/* SRC_CLOCK = SCLK_EPLL */
#define SPI0_SEL 6
#define SPI1_SEL 6
#define SPI2_SEL 6
#define AUDIO0_SEL 6
#define AUDIO1_SEL 6
#define AUDIO2_SEL 6
@ -395,9 +396,9 @@ struct exynos5_phy_control;
| (AUDIO0_RATIO << 20))
/* CLK_DIV_PERIC4 */
#define SPI2_PRE_RATIO 0x2
#define SPI1_PRE_RATIO 0x2
#define SPI0_PRE_RATIO 0x2
#define SPI2_PRE_RATIO 0x3
#define SPI1_PRE_RATIO 0x3
#define SPI0_PRE_RATIO 0x3
#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
| (SPI1_PRE_RATIO << 16) \
| (SPI0_PRE_RATIO << 8))