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exynos5420: Fix the way the rate of the input clock for i2c buses is found.

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The clock divider was being read from registers incorrectly which meant that
the periph rate was wrong.

BUG=chrome-os-partner:19420
TEST=Built and booted into depthcharge on pit.
BRANCH=None

Change-Id: Idb38374195a737fac2f096771929c8f1645d7247
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59729
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-06-22 19:43:40 -07:00 • committed by ChromeBot
commit 0dd1750cba
1 changed files with 2 additions and 3 deletions
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5
src/cpu/samsung/exynos5420/clock.c
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@ -196,9 +196,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
case PERIPH_ID_I2C9:
case PERIPH_ID_I2C10:
sclk = get_pll_clk(MPLL);
sub_div = ((readl(&clk->clk_div_top1) >> 24) & 0x7) + 1;
div = (readl(&clk->clk_div_top0) & 0x7) + 1;
return (sclk / sub_div) / div;
div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1;
return sclk / div;
default:
printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
return -1;