From 80ad8bb9bdc75f180e667861fed42a3844226bc5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 1 May 2014 13:53:49 -0700 Subject: [PATCH] broadwell: pmutil: Add new acpi_sci_irq() function This function will read the chipset register to determine the interrupt assigned for SCI in order to create the ACPI MADT IRQ override entry. BUG=chrome-os-partner:28234 TEST=None Change-Id: Idba2ab3d84fa843304d03b3e707c3678ed16e71e Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/199186 Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/pmutil.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index f0ca11b3fd..272731cd4f 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -422,3 +422,31 @@ void disable_gpe(u32 mask) gpe0_en &= ~mask; outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); } + +int acpi_sci_irq(void) +{ + int scis = pci_read_config32(PCH_DEV_LPC, ACPI_CNTL) & SCI_IRQ_SEL; + int sci_irq = 9; + + /* Determine how SCI is routed. */ + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +}