From 804aab3abb9ac5ad0b7123af4c558ccaa88316df Mon Sep 17 00:00:00 2001 From: Luca Lai Date: Tue, 4 Nov 2025 11:01:41 +0800 Subject: [PATCH] mb/google/fatcat/var/ruby: Modify usb3 port setting Modify usb3 port 0 and 1 settings by vendor's advices. BUG=b:446771934 TEST=Build and boot to OS, check usb3 functions work by lsusb -t. Change-Id: I9ed47ead1b2ef0b007897513ceb99e9460875bdc Signed-off-by: Luca Lai Reviewed-on: https://review.coreboot.org/c/coreboot/+/89883 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Eric Lai --- src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb index 2e5f29faa6..2de2dc082b 100644 --- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb @@ -32,8 +32,8 @@ chip soc/intel/pantherlake register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB) register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint - register "usb3_ports[0]" = "USB3_PORT_EMPTY" # no use - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 Type-A (DB) + register "usb3_ports[0]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #1 (MB) + register "usb3_ports[1]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #2 (DB) register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1