From 7da6c68eed14fb84af2f93e3fa5dc3bef602cb82 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 6 Feb 2025 09:34:20 +0100 Subject: [PATCH] soc/amd/common/block/graphics: Use vbt_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement vbt_get() on AMD and return the VBIOS location. This allows to drop the hardcoded addresses used in various places and return an address in DRAM that is reserved for FSP use. TEST: amd/birman+ still gets passed the correct VBIOS address. Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/86299 Reviewed-by: Jérémy Compostella Reviewed-by: Felix Held Tested-by: build bot (Jenkins) Reviewed-by: Ana Carolina Cabral --- src/drivers/intel/fsp2_0/silicon_init.c | 5 ++++ src/soc/amd/cezanne/fsp_s_params.c | 3 ++- src/soc/amd/common/block/graphics/graphics.c | 24 +++++++------------ .../amd/common/block/include/amdblocks/vbt.h | 22 +++++++++++++++++ src/soc/amd/glinda/fsp_s_params.c | 3 ++- src/soc/amd/mendocino/fsp_s_params.c | 3 ++- src/soc/amd/phoenix/fsp_s_params.c | 3 ++- src/soc/amd/picasso/fsp_s_params.c | 3 ++- 8 files changed, 46 insertions(+), 20 deletions(-) create mode 100644 src/soc/amd/common/block/include/amdblocks/vbt.h diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 1caf00ff73..fdac9f5b85 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -14,7 +14,12 @@ #include #include #include +#if CONFIG(SOC_AMD_COMMON) +#include +#endif +#if CONFIG(SOC_INTEL_COMMON) #include +#endif #include #include #include diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index b9770f3ef5..391461e2f7 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -13,7 +14,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 77420aebaa..f80484da8f 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include #include static bool vbios_loaded_from_cache = false; @@ -146,17 +146,11 @@ static const char *graphics_acpi_name(const struct device *dev) return "IGFX"; } -/* - * On AMD platforms the VBT is called ATOMBIOS and is always part of the - * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are - * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP - * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but - * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM - * notify is called. FSP expects a pointer to the PCI option rom instead - * a pointer to the ATOMBIOS table directly. - */ void *vbt_get(void) { + if (CONFIG(RUN_FSP_GOP)) + return (void *)(uintptr_t)PCI_VGA_RAM_IMAGE_START; + return NULL; } @@ -259,12 +253,12 @@ static void write_vbios_cache_to_fmap(void *unused) } /* copy from PCI_VGA_RAM_IMAGE_START to rdev */ - if (rdev_writeat(&rw_vbios_cache, (void *)PCI_VGA_RAM_IMAGE_START, 0, + if (rdev_writeat(&rw_vbios_cache, vbt_get(), 0, VBIOS_CACHE_FMAP_SIZE) != VBIOS_CACHE_FMAP_SIZE) printk(BIOS_ERR, "Failed to save vbios data to flash; rdev_writeat() failed.\n"); - /* copy modified vbios data from PCI_VGA_RAM_IMAGE_START to buffer before hashing */ - memcpy(vbios_data, (void *)PCI_VGA_RAM_IMAGE_START, VBIOS_CACHE_FMAP_SIZE); + /* copy modified vbios data to buffer before hashing */ + memcpy(vbios_data, vbt_get(), VBIOS_CACHE_FMAP_SIZE); /* save data hash to TPM NVRAM for validation on subsequent boots */ vbios_cache_update_hash(vbios_data, VBIOS_CACHE_FMAP_SIZE); @@ -279,8 +273,8 @@ static void write_vbios_cache_to_fmap(void *unused) */ void vbios_load_from_cache(void) { - /* copy cached vbios data from buffer to PCI_VGA_RAM_IMAGE_START */ - memcpy((void *)PCI_VGA_RAM_IMAGE_START, vbios_data, VBIOS_CACHE_FMAP_SIZE); + /* copy cached vbios data from buffer to address used by FSP */ + memcpy(vbt_get(), vbios_data, VBIOS_CACHE_FMAP_SIZE); /* mark cache as used so we know not to write it later */ vbios_loaded_from_cache = true; diff --git a/src/soc/amd/common/block/include/amdblocks/vbt.h b/src/soc/amd/common/block/include/amdblocks/vbt.h new file mode 100644 index 0000000000..05fc5e3433 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/vbt.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_BLOCK_VBT_H_ +#define _AMD_BLOCK_VBT_H_ + +/* + * On AMD platforms the VBT is called ATOMBIOS and is always part of the + * VGA Option ROM. As part of the FSP GOP init the ATOMBIOS tables are + * updated in place. Thus the VBIOS must be loaded into RAM before FSP GOP + * runs. The address of the VBIOS must be passed to FSP-S using UPDs, but + * loading of the VBIOS can be delayed until before FSP AFTER_PCI_ENUM + * notify is called. FSP expects a pointer to the PCI Option Rom instead of + * a pointer to the ATOMBIOS table directly. + * + * Returns a pointer to the VGA Option ROM in DRAM after checking + * prerequisites for Pre OS Graphics initialization. When returning + * non NULL the Option ROM might not be loaded at this address yet, + * but is guaranteed to be present at end of BS_DEV_RESOURCES phase. + */ +void *vbt_get(void); + +#endif diff --git a/src/soc/amd/glinda/fsp_s_params.c b/src/soc/amd/glinda/fsp_s_params.c index e03795792d..980eea8367 100644 --- a/src/soc/amd/glinda/fsp_s_params.c +++ b/src/soc/amd/glinda/fsp_s_params.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -15,7 +16,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 5c37334f5a..5393eba911 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -26,7 +27,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) * before FSP notify AFTER_PCI_ENUM. */ printk(BIOS_SPEW, "%s: not using VBIOS cache; running GOP driver.\n", __func__); - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/phoenix/fsp_s_params.c b/src/soc/amd/phoenix/fsp_s_params.c index 883cde0f89..9ce09f807f 100644 --- a/src/soc/amd/phoenix/fsp_s_params.c +++ b/src/soc/amd/phoenix/fsp_s_params.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -15,7 +16,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index d4cfa276c1..fd6f81767d 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -190,7 +191,7 @@ static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) * part of FSP GOP init. We can delay loading of the VBIOS until * before FSP notify AFTER_PCI_ENUM. */ - scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0; + scfg->vbios_buffer_addr = (uintptr_t)vbt_get(); } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)