From 7d3bf767cc873bf8ef029e0e0a75dc2f9b2fb33a Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Fri, 31 Oct 2025 15:44:50 +0800 Subject: [PATCH] soc/mediatek/mt8189: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record the watchdog timeout event, before triggering the reboot. Then, in the next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then a watchdog event will be added to the event log. The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be preserved across AP resets. However, for MT8189, the whole SRAM region will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB). Fortunately, the Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is also enabled. Therefore, even if WATCHDOG_TOMBSTONE data is cleared, the elog_handle_watchdog_tombstone() function can still obtain the correct watchdog reset reason from EC. On MT8189, L3C (used as SRAM_L2C) is powered on by default. Also, per MT8189 PMIC configuration, a SYSRSTB reset will retain the L3C power. Therefore, region data in SRAM_L2C can be preserved across AP resets. Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C. Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE. BUG=b:433636690, b:456672760 TEST=emerge-skywalker coreboot TEST=watchdog event added to eventlog on WDT timeout TEST=cbmem logs preserved on WDT timeout BRANCH=skywalker Change-Id: Id1cfc2700301ebb0b6399356b884b2473c883445 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/90171 Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin Reviewed-by: Chen-Tsung Hsieh --- src/soc/mediatek/mt8189/include/soc/memlayout.ld | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/soc/mediatek/mt8189/include/soc/memlayout.ld b/src/soc/mediatek/mt8189/include/soc/memlayout.ld index 7e77a816ed..a9c867a58a 100644 --- a/src/soc/mediatek/mt8189/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8189/include/soc/memlayout.ld @@ -4,9 +4,12 @@ SECTIONS { - /* MT8189 has 64KB SRAM. */ + /* + * MT8189 has 64KB SRAM. Per HW design, on SoC reset via GPIO + * AP_SYSRST_ODL (SYSRSTB), SRAM will be powered down. That means + * SRAM data will be lost across SoC resets. + */ SRAM_START(0x00100000) - WATCHDOG_TOMBSTONE(0x00100030, 4) /* * MCUPM uses the following regions to exchange data with kernel. @@ -58,7 +61,8 @@ SECTIONS DMA_COHERENT(0x020DC000, 4K) STACK(0x020DD000, 15K) TIMESTAMP(0x020E0C00, 1K) - PRERAM_CBMEM_CONSOLE(0x020E1000, 124K) + PRERAM_CBMEM_CONSOLE(0x020E1000, 123K) + WATCHDOG_TOMBSTONE(0x0020FFC00, 4) SRAM_L2C_END(0x02100000) DRAM_START(0x40000000)