diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 2a893a2daf..07f39593a0 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1118,6 +1118,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_B760: case PCI_DEVICE_ID_INTEL_HM770: case PCI_DEVICE_ID_INTEL_WM790: + case PCI_DEVICE_ID_INTEL_HM470: case PCI_DEVICE_ID_INTEL_C262: case PCI_DEVICE_ID_INTEL_C266: case PCI_DEVICE_ID_INTEL_ADL_P: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 23757ba630..c8fbdb4439 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -186,6 +186,7 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_HM470: *community_count = ARRAY_SIZE(cannonlake_pch_h_communities); *pad_stepping = 16; return cannonlake_pch_h_communities; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 5bd9a05949..0ed9b8331c 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -145,11 +145,17 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U, "10th generation (Icelake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U1, - "10th generation (Comet Lake family) Core Processor (Mobile)" }, + "10th generation (Comet Lake-U family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U2, - "10th generation (Comet Lake family) Core Processor (Mobile)" }, + "10th generation (Comet Lake-U family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U3, - "10th generation (Comet Lake family) Core Processor (Mobile)" }, + "10th generation (Comet Lake-U family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2, + "10th generation (Comet Lake-H family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2, + "10th generation (Comet Lake-H family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2, + "10th generation (Comet Lake-H family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE, "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP, @@ -435,6 +441,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM470, "HM470" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" }, @@ -617,6 +624,22 @@ static const struct { "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2, "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_S_1, + "Intel(R) CometLake-S GT1" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_S_2, + "Intel(R) CometLake-S GT1" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, + "Intel(R) CometLake-S GT2" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, + "Intel(R) CometLake-S GT2" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_H_1, + "Intel(R) CometLake-H GT1" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_H_2, + "Intel(R) CometLake-H GT1" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, + "Intel(R) CometLake-H GT2" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, + "Intel(R) CometLake-H GT2" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1, "Intel(R) AlderLake-S GT1" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1_2, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index c279d02e87..a9419e3431 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -224,6 +224,7 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_WM590 0x4389 #define PCI_DEVICE_ID_INTEL_QM580 0x438a #define PCI_DEVICE_ID_INTEL_HM570 0x438b +#define PCI_DEVICE_ID_INTEL_HM470 0x068d #define PCI_DEVICE_ID_INTEL_C252 0x438c #define PCI_DEVICE_ID_INTEL_C256 0x438d #define PCI_DEVICE_ID_INTEL_W580 0x438f @@ -399,6 +400,9 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2 0x9b44 /* Cometlake H 8+2 (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2 0x9b54 /* Cometlake H 6+2 (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2 0x9b64 /* Cometlake H 4+2 (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */ #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */ #define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */ @@ -506,6 +510,14 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78 #define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70 +#define PCI_DEVICE_ID_INTEL_CML_GT1_S_1 0x9BA5 +#define PCI_DEVICE_ID_INTEL_CML_GT1_S_2 0x9BA8 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0 0x9BC8 +#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0 0x9BC5 +#define PCI_DEVICE_ID_INTEL_CML_GT1_H_1 0x9BA4 +#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9BA2 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0 0x9BC2 +#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1 0x9BC4 /* Elkhart Lake */ #define PCI_DEVICE_ID_INTEL_EHL_GT1_1 0x4541 #define PCI_DEVICE_ID_INTEL_EHL_GT1_2 0x4551 diff --git a/util/inteltool/lpc.c b/util/inteltool/lpc.c index 4ce06ae5b9..9fbec66402 100644 --- a/util/inteltool/lpc.c +++ b/util/inteltool/lpc.c @@ -150,6 +150,23 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc) cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers); } break; + case PCI_DEVICE_ID_INTEL_HM470: + dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); + if (!dev) { + printf("LPC/eSPI interface not found.\n"); + return 1; + } + bc = pci_read_long(dev, SUNRISE_LPC_BC); + if (bc & (1 << 2)) { + printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n"); + cfg_registers = alderlake_espi_cfg_registers; + cfg_registers_size = ARRAY_SIZE(alderlake_espi_cfg_registers); + } else { + printf("Device 0:1f.0 is LPC (BC.LPC_ESPI=0)\n\n"); + cfg_registers = sunrise_lpc_cfg_registers; + cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers); + } + break; case PCI_DEVICE_ID_INTEL_ADL_N: dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0); if (!dev) { diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index bb7ad60617..608a95533a 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -229,6 +229,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_CML_U1: case PCI_DEVICE_ID_INTEL_CORE_CML_U2: case PCI_DEVICE_ID_INTEL_CORE_CML_U3: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 32afa714fc..06a09df3ca 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -227,6 +227,35 @@ static const io_register_t alderlake_dmi_registers[] = { { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask }; +/* 10th Generation Intel® Core™ Processors, Datasheet Volume 2 of 2, ID 615211 */ +static const io_register_t cometlake_dmi_registers[] = { + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration + { 0x44, 4, "DMIESD" }, // DMI Element Self Description + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description + { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address + { 0x84, 4, "LCAP" }, // Link Capabilities + { 0x88, 2, "LCTL" }, // Link Control + { 0x8A, 2, "LSTS" }, // DMI Link Status + { 0x98, 2, "LCTL2" }, // Link Control 2 + { 0x9A, 2, "LSTS2" }, // Link Status 2 +}; + /* * Egress Port Root Complex MMIO configuration space */ @@ -292,6 +321,12 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: + case PCI_DEVICE_ID_INTEL_CORE_CML_U1: + case PCI_DEVICE_ID_INTEL_CORE_CML_U2: + case PCI_DEVICE_ID_INTEL_CORE_CML_U3: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -433,6 +468,18 @@ int print_dmibar(struct pci_dev *nb) dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; + case PCI_DEVICE_ID_INTEL_CORE_CML_U1: + case PCI_DEVICE_ID_INTEL_CORE_CML_U2: + case PCI_DEVICE_ID_INTEL_CORE_CML_U3: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2: + dmi_registers = cometlake_dmi_registers; + size = ARRAY_SIZE(cometlake_dmi_registers); + dmibar_phys = pci_read_long(nb, 0x68); + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ + break; case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: @@ -555,6 +602,12 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4: case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1: + case PCI_DEVICE_ID_INTEL_CORE_CML_U1: + case PCI_DEVICE_ID_INTEL_CORE_CML_U2: + case PCI_DEVICE_ID_INTEL_CORE_CML_U3: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2: + case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 6d70905021..8654e32a89 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -141,6 +141,7 @@ void pcr_init(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_C252: case PCI_DEVICE_ID_INTEL_C256: case PCI_DEVICE_ID_INTEL_W580: + case PCI_DEVICE_ID_INTEL_HM470: case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 87fa38ffbc..a11cf5f2e8 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -125,6 +125,7 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH4M: case PCI_DEVICE_ID_INTEL_ICH5: case PCI_DEVICE_ID_INTEL_ADL_N: + case PCI_DEVICE_ID_INTEL_HM470: printf("This southbridge does not have RCBA.\n"); return 1; default: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index cba43ed10e..9c3d2f12f5 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -171,6 +171,53 @@ static const io_register_t elkhart_spi_bar_registers[] = { { 0x198, 4, "CSXE_WPR0 - Write Protected Range 0" }, }; +/* Intel® 400 Series Chipset Family Platform Controller Hub, 620855-002 */ +static const io_register_t cometlake_spi_bar_registers[] = { + { 0x00, 4, "BFPREG - BIOS Flash Primary Region" }, + { 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" }, + { 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" }, + { 0x08, 4, "FADDR - Flash Address" }, + { 0x0c, 4, "DLOCK - Discrete Lock Bits" }, + { 0x10, 4, "FDATA0 - Flash Data 0" }, + { 0x14, 4, "FDATA1 - Flash Data 1" }, + { 0x18, 4, "FDATA2 - Flash Data 2" }, + { 0x1c, 4, "FDATA3 - Flash Data 3" }, + { 0x20, 4, "FDATA4 - Flash Data 4" }, + { 0x24, 4, "FDATA5 - Flash Data 5" }, + { 0x28, 4, "FDATA6 - Flash Data 6" }, + { 0x2c, 4, "FDATA7 - Flash Data 7" }, + { 0x30, 4, "FDATA8 - Flash Data 8" }, + { 0x34, 4, "FDATA9 - Flash Data 9" }, + { 0x38, 4, "FDATA10 - Flash Data 10" }, + { 0x3c, 4, "FDATA11 - Flash Data 11" }, + { 0x40, 4, "FDATA12 - Flash Data 12" }, + { 0x44, 4, "FDATA13 - Flash Data 13" }, + { 0x48, 4, "FDATA14 - Flash Data 14" }, + { 0x4c, 4, "FDATA15 - Flash Data 15" }, + { 0x50, 4, "FRACC - Flash Region Access Permissions" }, + { 0x54, 4, "FREG0 - Flash Region 0" }, + { 0x58, 4, "FREG1 - Flash Region 1" }, + { 0x5c, 4, "FREG2 - Flash Region 2" }, + { 0x60, 4, "FREG3 - Flash Region 3" }, + { 0x64, 4, "FREG4 - Flash Region 4" }, + { 0x68, 4, "FREG5 - Flash Region 5" }, + { 0x84, 4, "FPR0 - Flash Protected Range 0" }, + { 0x88, 4, "FPR1 - Flash Protected Range 1" }, + { 0x8c, 4, "FPR2 - Flash Protected Range 2" }, + { 0x90, 4, "FPR3 - Flash Protected Range 3" }, + { 0x94, 4, "FPR4 - Flash Protected Range 4" }, + { 0x98, 4, "GPR0 - Global Protected Range 0" }, + { 0xb0, 4, "SFRACC - Secondary Flash Region Access Permissions" }, + { 0xb4, 4, "FDOC - Flash Descriptor Observability Control" }, + { 0xb8, 4, "FDOD - Flash Descriptor Observability Data" }, + { 0xc0, 4, "AFC - Additional Flash Control" }, + { 0xc4, 4, "SFDP0_VSCC0 - Vendor Specific Component Capabilities for Component 0" }, + { 0xc8, 4, "SFDP1_VSCC1 - Vendor Specific Component Capabilities for Component 1" }, + { 0xcc, 4, "PTINX - Parameter Table Index" }, + { 0xd0, 4, "PTDATA - Parameter Table Data" }, + { 0xd4, 4, "SBRS - SPI Bus Requester Status" }, +}; + static int print_bioscntl(struct pci_dev *sb) { int i, size = 0; @@ -303,6 +350,7 @@ static int print_bioscntl(struct pci_dev *sb) size = ARRAY_SIZE(pch_bios_cntl_registers); break; case PCI_DEVICE_ID_INTEL_ADL_N: + case PCI_DEVICE_ID_INTEL_HM470: bios_cntl = pci_read_byte(sb, 0xdc); bios_cntl_register = adl_pch_bios_cntl_registers; size = ARRAY_SIZE(adl_pch_bios_cntl_registers); @@ -330,13 +378,29 @@ static int print_bioscntl(struct pci_dev *sb) return 0; } +static int get_espibar_phys(struct pci_dev *sb, struct pci_access *pacc, uint8_t func, uint8_t offset, uint32_t mask, uint32_t *addr) { + struct pci_dev *spidev; + + if (!(spidev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, func))) { + fprintf(stderr, "Error: no spi device 0:31.%x\n", func); + return 1; + } + + *addr = pci_read_long(spidev, offset) & mask; + if (!*addr) { + fprintf(stderr, "Error: no valid bar 0 of device 0:31.%x found %x\n", func, *addr); + return 1; + } + + return 0; +} + static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) { int i, size = 0, rcba_size = 0x4000; volatile uint8_t *rcba; uint32_t rcba_phys; const io_register_t *spi_register = NULL; uint32_t spibaroffset; - struct pci_dev *spidev; printf("\n============= SPI Bar ==============\n\n"); @@ -461,23 +525,22 @@ static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) { break; case PCI_DEVICE_ID_INTEL_EHL: /* the southbridge is the eSPI controller, we need to get the SPI flash controller */ - if (!(spidev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 5))) { - perror("Error: no spi device 0:31.5\n"); - return 1; - } - - rcba_phys = ((uint64_t)pci_read_long(spidev, 0x10) & 0xfffff000); - rcba_size = 4096; - if (!rcba_phys) { - fprintf(stderr, "Error: no valid bar 0 of device 0:31.5 found %x %x\n", rcba_phys, rcba_size); - return 1; - } - /* this is not rcba, but we keep it to use common code */ + if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys)) + return 1; + rcba_size = 4096; spibaroffset = 0; spi_register = elkhart_spi_bar_registers; size = ARRAY_SIZE(elkhart_spi_bar_registers); break; + case PCI_DEVICE_ID_INTEL_HM470: + if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys)) + return 1; + rcba_size = 4096; + spibaroffset = 0; + spi_register = cometlake_spi_bar_registers; + size = ARRAY_SIZE(cometlake_spi_bar_registers); + break; case PCI_DEVICE_ID_INTEL_ICH: case PCI_DEVICE_ID_INTEL_ICH0: case PCI_DEVICE_ID_INTEL_ICH2: