From 7c1a9ba9b44cb1596b6c27e2fc06303b753541df Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 22 Jan 2025 16:26:22 +0530 Subject: [PATCH] soc/intel/pantherlake: Add platform debug option for FSP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously, DCI was enabled unconditionally, which could interfere with the USB data path when connected behind a powered hub and/or servo v4.1 debug connector. This patch sets DciEn parameter based on the selected platform debug option. If TraceHub is enabled, DciEn is set to 1. Otherwise, it is set to 0. BUG=b:384453901 TEST=Able to boot google/fatcat. Change-Id: Ie77a4cc8073fdffb1b26f92597c67465e15e21d8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/86104 Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella Reviewed-by: Pranava Y N Reviewed-by: Bora Guvendik Reviewed-by: Jamie Ryu --- src/soc/intel/pantherlake/chip.h | 17 +++++++++++++++++ src/soc/intel/pantherlake/romstage/fsp_params.c | 12 +++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 5846037c95..e879fadb60 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -121,6 +121,23 @@ enum lpm_state_mask { | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, }; +/* Platform Debug Option using HW interface + * + * 0: Disabled, + * 2: Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix, + * 4: Enabled Trace ready: TraceHub is enabled and allowed S0ix, + * 6: Enabled Trace power off: TraceHub is powergated, provide setting close to functional + * low power state, + * 7: User needs to configure Advanced Debug Settings manually. (only applicable for devices + * with BIOS Setup Menu option present. + */ +enum platform_hw_debug_option { + HW_DEBUG_DISABLE = 0, + HW_DEBUG_TRACEHUB_ACTIVE = BIT(1), + HW_DEBUG_TRACEHUB_READY = BIT(2), + HW_DEBUG_TRACEHUB_POWEROFF = BIT(2) | BIT(1), +}; + /* * As per definition from FSP header: * - [0] for IA diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 033c4ea25d..2bb4d21c6a 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -253,7 +253,17 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, m_cfg->PlatformDebugOption = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT; m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG); - m_cfg->DciEn = 1; + + switch (CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT) { + case HW_DEBUG_TRACEHUB_ACTIVE: + case HW_DEBUG_TRACEHUB_READY: + case HW_DEBUG_TRACEHUB_POWEROFF: + m_cfg->DciEn = 1; + break; + case HW_DEBUG_DISABLE: + m_cfg->DciEn = 0; + break; + } } static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg,