From 76d45a8219373cfe6219ff1ee7b9b8995a69302b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 9 Jul 2025 10:40:20 +0200 Subject: [PATCH] soc/amd/genoa_poc/root_complex.c: Explain the order of IOHCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At first glance the order of IOHCs seems peculiar. However, the order is not random. Explain the reasoning of the IOHC order in the comment. Change-Id: Ic8e567d48a0f8d95ff9785cdd0c5489ea3016f1a Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/88369 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Alicja Michalska --- src/soc/amd/genoa_poc/root_complex.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/amd/genoa_poc/root_complex.c b/src/soc/amd/genoa_poc/root_complex.c index 3171febe9f..868e9c5db8 100644 --- a/src/soc/amd/genoa_poc/root_complex.c +++ b/src/soc/amd/genoa_poc/root_complex.c @@ -4,6 +4,16 @@ #include #include +/* + * The order of IOHCs here is not random. They are sorted so that: + * 1. The First IOHC is the one with primary FCH. We want the LPC/SMBUS + * devices be on bus 0. + * 2. The rest of IOHCs are listed in an order so that ECAM MMIO region is one + * continuous block for all domains. + * + * AGESA/OpenSIL sets up the PCI configuration decoding ranges in line with + * this. + */ static const struct domain_iohc_info iohc_info[] = { [0] = { .fabric_id = 0x22,