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tegra124: enable JTAG on lp0 exit

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On SECURITY_MODE (also known ODM Production mode), JTAG is disabled by
BootROM. We need this setting to reenable JTAG on lp0 exit.

BUG=None
TEST=Burn SECURITY_MODE fuse, build chip specific BCT.
         wait for Penny to verify.

Change-Id: I81c6e3bc7c74d7915110f7bdd115c323b3a6b96c
Reviewed-on: https://chromium-review.googlesource.com/186677
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Penny Chiu <pchiu@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Jimmy Zhang 2014-02-14 16:24:05 -08:00 • committed by chrome-internal-fetch
commit 81f8746b3a
1 changed files with 16 additions and 0 deletions
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16
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
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@ -24,6 +24,7 @@ enum {
CLK_RST_BASE = 0X60006000,
FLOW_CTLR_BASE = 0X60007000,
TEGRA_EVP_BASE = 0x6000f000,
APB_MISC_BASE = 0x70000000,
PMC_CTLR_BASE = 0X7000e400,
MC_CTLR_BASE = 0X70019000,
SYSCTR_CTLR_BASE = 0X700f0000
@ -38,6 +39,12 @@ enum {
};
/* APB Misc JTAG Configuration Register */
static uint32_t *misc_pp_config_ctl_ptr = (void *)(APB_MISC_BASE + 0x24);
enum {
PP_CONFIG_CTL_JTAG = 0x1 << 6
};
/* Timer registers. */
static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10);
@ -315,6 +322,12 @@ static unsigned get_osc_freq(void)
}
/* Jtag configuration. */
static void enable_jtag(void)
{
write32(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
}
/* Clock configuration. */
@ -543,6 +556,9 @@ void lp0_resume(void)
if (read32(up_tag_ptr) != UP_TAG_AVP)
reset();
// Enable JTAG
enable_jtag();
config_oscillator();
// Tell the flow controller which cluster to wake up. The default is