From 75ac3d4d1aa7f628eac2b34be86359984627de54 Mon Sep 17 00:00:00 2001 From: Li-Ta Lo Date: Wed, 17 Jan 2001 08:18:38 +0000 Subject: [PATCH] enable CPU pipeline and disable DRAM delay --- src/northsouthbridge/sis/630/630_regs.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northsouthbridge/sis/630/630_regs.inc b/src/northsouthbridge/sis/630/630_regs.inc index a182874a85..9ac3f9f1f1 100644 --- a/src/northsouthbridge/sis/630/630_regs.inc +++ b/src/northsouthbridge/sis/630/630_regs.inc @@ -39,7 +39,7 @@ northbridge_init_table: /* SiS 630 specific registers. See SiS 630 Registers Recommended Setting */ /* Host Control Interface */ - .byte 0x50, 0x9C # + .byte 0x50, 0x9E # .byte 0x51, 0x00 # /* DRAM Control */ @@ -48,7 +48,7 @@ northbridge_init_table: .byte 0x54, 0x00 # 0x00 -> 66/100 MHZ, 0x08 -> 133 MHZ .byte 0x55, 0x29 # 0x29 -> 66/100 MHZ, 0x1D -> 133 MHZ - .byte 0x56, 0x80 # 0x00 -> 66 MHZ, 0x80 -> 100/133 MHZ + .byte 0x56, 0x00 # 0x00 -> 66 MHZ, 0x80 -> 100/133 MHZ .byte 0x57, 0x00 # 0x00 -> 100 MHZ 0x01 -> 133 MHZ /* Pre-driver Slew Rate/Current Driving Control */