From 74ee80d2074c53114533b4217e7ba87344b00acc Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 2 Dec 2024 14:22:25 +0100 Subject: [PATCH] soc/intel/xeon_sp/cpx: Fix register lock Do not use a define for a PCI register to lock a MSR. The defines will be moved in the following commit to it's own header, preventing the use in CPX CPU init. Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/85439 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/cpx/cpu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index d90b8b508e..ae3f0fb423 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -115,10 +115,8 @@ static void each_cpu_init(struct device *cpu) set_vmx_and_lock(); set_aesni_lock(); - /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions - Lock Turbo. Did FSP-S set this up??? */ msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); - msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + msr.lo |= BIT31; /* Lock it */ wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); }