diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 95258eaa85..c126baac62 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -66,6 +66,7 @@ enum clk_ctl_lpass_aon_cc_pll_user_ctl_x1p42100 {
 	AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100 = 2,
 	AON_CC_PLL_POST_DIV_EVEN_SHFT_X1P42100 = 10,
 	AON_CC_PLL_POST_DIV_ODD_SHFT_X1P42100 = 14,
+	AON_CC_PLL_ENABLE_VOTE_RUN = 25
 };
 
 enum clk_pll_src {
@@ -280,16 +281,19 @@ struct x1p42100_lpass_aon_cc {
 	u32 va_mem0_cbcr;
 	u8 _res1[0x2c];
 	u32 lpass_audio_hm_gdscr;
-	u8 _res2[0x8F78];
+	u8 _res2[0x2f6c];
+	u32 lpass_hm_collapse_vote_for_q6;
+	u8 _res3[0x6008];
 	u32 va_2x_cbcr;
-	u8 _res3[0x4];
+	u8 _res4[0x4];
 	u32 va_cbcr;
-	u8 _res4[0xffc];
+	u8 _res5[0xffc];
 	u32 tx_mclk_cbcr;
 };
 
 check_member(x1p42100_lpass_aon_cc, va_mem0_cbcr, 0x9060);
 check_member(x1p42100_lpass_aon_cc, lpass_audio_hm_gdscr, 0x9090);
+check_member(x1p42100_lpass_aon_cc, lpass_hm_collapse_vote_for_q6, 0xc000);
 check_member(x1p42100_lpass_aon_cc, va_2x_cbcr, 0x1200C);
 check_member(x1p42100_lpass_aon_cc, va_cbcr, 0x12014);
 check_member(x1p42100_lpass_aon_cc, tx_mclk_cbcr, 0x13014);
diff --git a/src/soc/qualcomm/x1p42100/include/soc/lpass.h b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
index 79439e4ba7..0b5a8bd4dd 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/lpass.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/lpass.h
@@ -8,7 +8,8 @@
 /* LPASS AON CC PLL Settings */
 #define HAL_CLK_LPASS_AON_CC_PLL_L_VALUE	0x00000020
 #define HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE	0x00000000
-#define HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE	0x00000044
+#define HAL_CLK_LPASS_AON_CC_PLL_RING_CAL_L_VALUE	(0x44 << 16)
+#define HAL_CLK_LPASS_AON_CC_PLL_PROC_CAL_L_VALUE	(0x44 << 24)
 #define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL	0x20485699
 #define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U	0x00182261
 #define HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL_U1	0x82AA299C
@@ -23,5 +24,8 @@
 #define HW_CTL					BIT(1)
 #define GDSC_ENABLE_BIT				0
 
+#define LPASS_CORE_HM_VOTE_POWER_ON		0x0
+#define GDSC_PWR_ON				BIT(31)
+
 #define BCM_LP0_VOTE_VALUE			0x60004001
 #endif /* _SOC_QUALCOMM_X1P42100_LPASS_H_ */
diff --git a/src/soc/qualcomm/x1p42100/lpass.c b/src/soc/qualcomm/x1p42100/lpass.c
index 437a888cb0..fb96616dbd 100644
--- a/src/soc/qualcomm/x1p42100/lpass.c
+++ b/src/soc/qualcomm/x1p42100/lpass.c
@@ -13,13 +13,14 @@ static enum cb_err lpass_aon_cc_pll_enable(void)
 
 	pll_cfg.reg_mode = &lpass_aon_cc_pll->pll_mode;
 	pll_cfg.reg_l = &lpass_aon_cc_pll->pll_l_val;
-	pll_cfg.l_val = HAL_CLK_LPASS_AON_CC_PLL_L_VALUE;
+	pll_cfg.l_val = HAL_CLK_LPASS_AON_CC_PLL_L_VALUE |
+		HAL_CLK_LPASS_AON_CC_PLL_PROC_CAL_L_VALUE |
+			HAL_CLK_LPASS_AON_CC_PLL_RING_CAL_L_VALUE;
 
 	pll_cfg.reg_alpha = &lpass_aon_cc_pll->pll_alpha_val;
 	pll_cfg.alpha_val = HAL_CLK_LPASS_AON_CC_PLL_ALPHA_VALUE;
 
 	pll_cfg.reg_cal_l = &lpass_aon_cc_pll->pll_l_val;
-	pll_cfg.cal_l_val = HAL_CLK_LPASS_AON_CC_PLL_CAL_L_VALUE;
 
 	pll_cfg.reg_config_ctl = &lpass_aon_cc_pll->pll_config_ctl;
 	pll_cfg.config_ctl_val = HAL_CLK_LPASS_AON_CC_PLL_CONFIG_CTL;
@@ -45,10 +46,8 @@ static enum cb_err lpass_aon_cc_pll_enable(void)
 	write32(&lpass_aon_cc_pll->pll_test_ctl_u1, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U1);
 	write32(&lpass_aon_cc_pll->pll_test_ctl_u2, HAL_CLK_LPASS_AON_CC_PLL_TEST_CTL_U2);
 
-	if (lucidole_pll_enable(&pll_cfg) != CB_SUCCESS) {
-		printk(BIOS_ERR, "LPASS: AON CC PLL enable failed\n");
-		return CB_ERR;
-	}
+	setbits32(&lpass_aon_cc_pll->pll_user_ctl, BIT(AON_CC_PLL_ENABLE_VOTE_RUN));
+	setbits32(&lpass_aon_cc_pll->pll_mode, BIT(PLL_RESET_SHFT));
 
 	setbits32(&lpass_aon_cc_pll->pll_user_ctl, (BIT(AON_CC_PLL_PLLOUT_EVEN_SHFT_X1P42100) |
 				BIT(AON_CC_PLL_PLLOUT_ODD_SHFT_X1P42100)));
@@ -66,8 +65,10 @@ static enum cb_err lpass_setup_core_infrastructure(void)
 
 	setbits32(&lpass_core_gdsc->lpass_top_cc_lpass_core_sway_ahb_ls_cbcr, HW_CTL);
 
-	if (enable_and_poll_gdsc_status(&lpass_core_gdsc->core_hm_gdscr) != CB_SUCCESS) {
-		printk(BIOS_ERR, "LPASS: Failed to enable Core HM GDSC\n");
+	write32(&lpass_aon_cc->lpass_hm_collapse_vote_for_q6, LPASS_CORE_HM_VOTE_POWER_ON);
+
+	if (!wait_us(150000, !(read32(&lpass_core_gdsc->core_hm_gdscr) & GDSC_PWR_ON))) {
+		printk(BIOS_ERR, "LPASS: Core HM GDSC PWR_ON timeout after vote\n");
 		return CB_ERR;
 	}
 
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index 78fa43a175..df4e803627 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -5,6 +5,7 @@
 #include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
 #include <soc/pcie.h>
+#include <soc/clock.h>
 #include <soc/cpucp.h>
 #include <program_loading.h>
 
@@ -89,6 +90,7 @@ static void soc_init(struct device *dev)
 {
 	cpucp_fw_load_reset();
 	qtee_fw_config_load();
+	lpass_init();
 }
 
 static struct device_operations soc_ops = {