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This patch changes all occurrences of pci_dev_set_resources ->

Browse source 
pci_set_resources.  There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
 
Signed-off-by: Myles Watson <mylesgw@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2008-11-24 14:06:10 +00:00
commit 72c2e85313
59 changed files with 104 additions and 101 deletions
Download patch file Download diff file Expand all files Collapse all files

2
device/agp_device.c
View file

@ -61,7 +61,7 @@ static const struct pci_operations agp_bus_ops_pci = {
const struct device_operations default_agp_ops_bus = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.set_resources = pci_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = 0,
.scan_bus = agp_scan_bridge,

2
device/cardbus_device.c
View file

@ -244,7 +244,7 @@ unsigned int cardbus_scan_bridge(struct device *dev, unsigned int max)
const struct device_operations default_cardbus_ops_bus = {
.phase3_scan = cardbus_scan_bridge,
.phase4_read_resources = cardbus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = cardbus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,

2
device/hypertransport.c
View file

@ -638,7 +638,7 @@ static const struct pci_operations ht_bus_ops_pci = {
const struct device_operations default_ht_ops_bus = {
.phase3_scan = ht_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,

6
device/pci_device.c
View file

@ -567,7 +567,7 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
return;
}
void pci_dev_set_resources(struct device *dev)
void pci_set_resources(struct device *dev)
{
struct resource *resource, *last;
unsigned int link;
@ -742,7 +742,7 @@ const struct pci_operations pci_dev_ops_pci = {
const struct device_operations default_pci_ops_dev = {
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pci_dev_init,
.phase3_scan = 0,
@ -757,7 +757,7 @@ const struct pci_operations pci_bus_ops_pci = {
const struct device_operations default_pci_ops_bus = {
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,

2
device/pcie_device.c
View file

@ -64,7 +64,7 @@ static const struct pci_operations pcie_bus_ops_pci = {
const struct device_operations default_pcie_ops_bus = {
.phase3_scan = pcie_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,

2
device/pcix_device.c
View file

@ -142,7 +142,7 @@ struct pci_operations pcix_bus_ops_pci = {
struct device_operations default_pcix_ops_bus = {
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.phase3_scan = pcix_scan_bridge,

2
include/device/pci.h
View file

@ -78,7 +78,7 @@ extern const struct pci_operations pci_bus_ops_pci;
void pci_dev_read_resources(struct device * dev);
void pci_bus_read_resources(struct device * dev);
void pci_dev_set_resources(struct device * dev);
void pci_set_resources(struct device * dev);
void pci_dev_enable_resources(struct device * dev);
void pci_bus_enable_resources(struct device * dev);
void pci_bus_reset(struct bus *bus);

2
mainboard/emulation/qemu-x86/vga.c
View file

@ -53,7 +53,7 @@ struct device_operations qemuvga_pci_ops_dev = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = setup_onboard,
.ops_pci = &pci_dev_ops_pci,

2
mainboard/kontron/986lcd-m/rtl8168.c
View file

@ -43,7 +43,7 @@ struct device_operations nic_ops = {
.device = 0x8168}}},
.constructor = default_device_constructor,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = nic_init,
.ops_pci = &pci_dev_ops_pci,

3
northbridge/intel/i945/northbridge.c
View file

@ -197,6 +197,7 @@ static void mc_read_resources(struct device * dev)
pci_dev_read_resources(dev);
#warning After we fix the allocator we need to fix this!
/* So, this is one of the big mysteries in the coreboot resource
* allocator. This resource should make sure that the address space
* of the PCIe memory mapped config space bar. But it does not.
@ -226,7 +227,7 @@ static void mc_set_resources(struct device * dev)
}
/* And call the normal set_resources */
pci_dev_set_resources(dev);
pci_set_resources(dev);
}
static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device)

2
northbridge/via/cn700/agp.c
View file

@ -108,7 +108,7 @@ struct device_operations cn700_agp = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
//.phase4_set_resources = pci_dev_set_resources,
//.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = agp_init,
};

2
northbridge/via/cn700/pci.c
View file

@ -55,7 +55,7 @@ struct device_operations cn700_pci_bridge = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
//.phase4_set_resources = pci_dev_set_resources,
//.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pci_bridge_init,
};

2
northbridge/via/cn700/vga.c
View file

@ -73,7 +73,7 @@ struct device_operations cn700_vga = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = vga_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = vga_init,
};

4
southbridge/amd/amd8111/ac97.c
View file

@ -46,7 +46,7 @@ struct device_operations ac97audio = {
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,
@ -60,7 +60,7 @@ struct device_operations ac97modem = {
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,

2
southbridge/amd/amd8111/acpi.c
View file

@ -233,7 +233,7 @@ struct device_operations acpi = {
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = acpi_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = acpi_enable_resources,
.phase6_init = acpi_init,
.ops_pci = &lops_pci,

2
southbridge/amd/amd8111/ide.c
View file

@ -80,7 +80,7 @@ struct device_operations amd8111_ide = {
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &lops_pci

2
southbridge/amd/amd8111/lpc.c
View file

@ -215,7 +215,7 @@ struct device_operations amd8111_lpc = {
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = amd8111_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = amd8111_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &lops_pci,

2
southbridge/amd/amd8111/nic.c
View file

@ -101,7 +101,7 @@ struct device_operations amd8111_nic = {
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = nic_init,
.ops_pci = &lops_pci,

2
southbridge/amd/amd8111/pci.c
View file

@ -77,7 +77,7 @@ struct device_operations amd8111_pci = {
.phase3_scan = pci_scan_bridge,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
};

2
southbridge/amd/amd8111/smbus.c
View file

@ -55,7 +55,7 @@ struct device_operations amd8111_smbus = {
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,

2
southbridge/amd/amd8111/usb.c
View file

@ -52,7 +52,7 @@ struct device_operations amd8111_usb = {
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci

2
southbridge/amd/amd8111/usb2.c
View file

@ -51,7 +51,7 @@ struct device_operations amd8111_usb2 = {
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_usb2_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
};

4
southbridge/amd/amd8132/amd8132_bridge.c
View file

@ -340,7 +340,7 @@ static void bridge_set_resources(struct device *dev)
report_resource_stored(dev, res, "including NPUML");
}
pci_dev_set_resources(dev);
pci_set_resources(dev);
}
struct device_operations amd8132_pcix = {
@ -420,7 +420,7 @@ struct device_operations amd8132_apic = {
.phase3_scan = 0,
.phase3_chip_setup_dev = ioapic_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = amd8132_ioapic_init,
.ops_pci = &pci_ops_pci_dev,

4
southbridge/amd/amd8151/amd8151_agp3.c
View file

@ -47,7 +47,7 @@ struct device_operations amd8151_agp3bridge = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = agp3bridge_init,
};
@ -82,7 +82,7 @@ struct device_operations amd8151_agp3dev = {
.constructor = default_device_constructor,
.phase4_enable_disable = agp3dev_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &pci_dev_ops_pci,

4
southbridge/amd/cs5536/cs5536.c
View file

@ -696,7 +696,7 @@ struct device_operations cs5536_ops = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = cs5536_pci_dev_enable_resources,
.phase6_init = southbridge_init,
};
@ -709,7 +709,7 @@ struct device_operations cs5536_ide = {
#warning FIXME: what has to go in phase3_scan?
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &pci_dev_ops_pci,

3
southbridge/amd/rs690/gfx.c
View file

@ -109,8 +109,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
static void rs690_gfx_set_resources(struct device *dev)
{
#warning This does nothing. Implement it or remove it.
printk(BIOS_INFO, "rs690_gfx_set_resources.\n");
pci_dev_set_resources(dev);
pci_set_resources(dev);
}
/*

2
southbridge/amd/rs690/ht.c
View file

@ -88,7 +88,7 @@ struct device_operations rs690_ht = {
.phase3_scan = 0,
.phase3_chip_setup_dev = rs690_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,

16
southbridge/amd/rs690/pcie.c
View file

@ -402,7 +402,7 @@ struct device_operations rs690_pcie = {
.phase3_scan = pci_scan_bridge,
.phase3_chip_setup_dev = rs690_enable,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@ -416,7 +416,7 @@ struct device_operations rs690_pcie2 = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@ -429,7 +429,7 @@ struct device_operations rs690_pcie3 = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@ -442,7 +442,7 @@ struct device_operations rs690_pcie4 = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@ -455,7 +455,7 @@ struct device_operations rs690_pcie5 = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@ -468,7 +468,7 @@ struct device_operations rs690_pcie6 = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@ -481,7 +481,7 @@ struct device_operations rs690_pcie7 = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@ -494,7 +494,7 @@ struct device_operations rs690_pcie8 = {
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,

4
southbridge/amd/sb600/ac97.c
View file

@ -40,7 +40,7 @@ struct device_operations ac97audio = {
.phase3_scan = 0,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,
@ -54,7 +54,7 @@ struct device_operations ac97modem = {
.phase3_scan = 0,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,

2
southbridge/amd/sb600/hda.c
View file

@ -281,7 +281,7 @@ struct device_operations sb600_hda = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = hda_init,
.ops_pci = &lops_pci

2
southbridge/amd/sb600/ide.c
View file

@ -72,7 +72,7 @@ struct device_operations sb600_ide = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &lops_pci

2
southbridge/amd/sb600/lpc.c
View file

@ -215,7 +215,7 @@ struct device_operations sb600_lpc = {
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = sb600_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = sb600_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &lops_pci

2
southbridge/amd/sb600/pci.c
View file

@ -132,7 +132,7 @@ struct device_operations sb600_pci = {
.phase3_scan = pci_scan_bridge,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.reset_bus = pci_bus_reset,

2
southbridge/amd/sb600/sata.c
View file

@ -194,7 +194,7 @@ struct device_operations sb600_sata = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
.ops_pci = &lops_pci

3
southbridge/amd/sb600/sm.c
View file

@ -376,11 +376,12 @@ static void sb600_sm_read_resources(struct device * dev)
compact_resources(dev);
}
static void sb600_sm_set_resources(struct device *dev)
{
struct resource *res;
pci_dev_set_resources(dev);
pci_set_resources(dev);
res = find_resource(dev, 0x74);
pci_write_config32(dev, 0x74, res->base | 1 << 3);

2
southbridge/amd/sb600/usb.c
View file

@ -143,7 +143,7 @@ static void usb_set_resources(struct device *dev)
old_debug = get_ehci_debug();
set_ehci_debug(0);
#endif
pci_dev_set_resources(dev);
pci_set_resources(dev);
#ifdef CONFIG_USBDEBUG_DIRECT
res = find_resource(dev, 0x10);

6
southbridge/intel/i82371eb/i82371eb.c
View file

@ -93,7 +93,7 @@ struct device_operations i82371eb_isa = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = i82371eb_isa_init,
.ops_pci = &pci_dev_ops_pci,
@ -105,7 +105,7 @@ struct device_operations i82371eb_ide = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = i82371eb_ide_init,
.ops_pci = &pci_dev_ops_pci,
@ -117,7 +117,7 @@ struct device_operations i82371eb_acpi = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = i82371eb_acpi_init,
.ops_pci = &pci_dev_ops_pci,

4
southbridge/intel/i82801gx/ac97.c
View file

@ -49,7 +49,7 @@ struct device_operations ac97audio = {
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ac97_audio_init,
.ops_pci = &pci_dev_ops_pci,
@ -65,7 +65,7 @@ struct device_operations ac97modem = {
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ac97_modem_init,
.ops_pci = &pci_dev_ops_pci,

2
southbridge/intel/i82801gx/ide.c
View file

@ -97,7 +97,7 @@ struct device_operations i82801gx_ide = {
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = ide_init,
.ops_pci = &pci_dev_ops_pci,

6
southbridge/intel/i82801gx/lpc.c
View file

@ -343,7 +343,7 @@ struct device_operations ich7_ich7r_ich7dh_lpc = {
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = i82801gx_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = i82801gx_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &pci_ops,
@ -360,7 +360,7 @@ struct device_operations ich7m_ich7u_lpc = {
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = i82801gx_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = i82801gx_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &pci_ops,
@ -376,7 +376,7 @@ struct device_operations ich7m_dh_lpc = {
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = i82801gx_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = i82801gx_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &pci_ops,

2
southbridge/intel/i82801gx/nic.c
View file

@ -44,7 +44,7 @@ struct device_operations i82801gx_nic= {
.device = 0x27dc}}},
.constructor = default_device_constructor,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = nic_init,
.ops_pci = &pci_dev_ops_pci,

4
southbridge/intel/i82801gx/pci.c
View file

@ -132,7 +132,7 @@ struct device_operations i82801g_pci = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = ich_pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@ -148,7 +148,7 @@ struct device_operations i82801gmu_pci = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = ich_pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,

12
southbridge/intel/i82801gx/pcie.c
View file

@ -89,7 +89,7 @@ struct device_operations i82801gx_pcie_port1 = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@ -104,7 +104,7 @@ struct device_operations i82801gx_pcie_port2 = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@ -119,7 +119,7 @@ struct device_operations i82801gx_pcie_port3 = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@ -134,7 +134,7 @@ struct device_operations i82801gx_pcie_port4 = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@ -149,7 +149,7 @@ struct device_operations i82801gx_pcie_port5 = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@ -164,7 +164,7 @@ struct device_operations i82801gx_pcie_port6 = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,

4
southbridge/intel/i82801gx/sata.c
View file

@ -150,7 +150,7 @@ struct device_operations i82801gx_sata_normal_driver = {
.reset_bus = pci_bus_reset,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
.ops_pci = &pci_dev_ops_pci,
@ -198,4 +198,4 @@ static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27c6,
};
#endif
#endif

2
southbridge/intel/i82801gx/smbus.c
View file

@ -56,7 +56,7 @@ struct device_operations i82801gx_smbus = {
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.ops_pci = &pci_dev_ops_pci,
.ops_smbus_bus = &lops_smbus_bus,

8
southbridge/intel/i82801gx/usb.c
View file

@ -56,7 +56,7 @@ struct device_operations i82801gb_usb1 = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,
@ -70,7 +70,7 @@ struct device_operations i82801gb_usb2 = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,
@ -84,7 +84,7 @@ struct device_operations i82801gb_usb3 = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,
@ -98,7 +98,7 @@ struct device_operations i82801gb_usb4 = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,

2
southbridge/intel/i82801gx/usb_ehci.c
View file

@ -80,7 +80,7 @@ struct device_operations i82801gx_usb_ehci = {
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = usb_ehci_init,
.ops_pci = &lops_pci,

2
southbridge/nvidia/mcp55/ide.c
View file

@ -77,7 +77,7 @@ struct device_operations mcp55_ide = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &mcp55_pci_dev_ops_pci,

16
southbridge/nvidia/mcp55/lpc.c
View file

@ -345,7 +345,7 @@ struct device_operations mcp55_lpc = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -358,7 +358,7 @@ struct device_operations mcp55_pro = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -371,7 +371,7 @@ struct device_operations mcp55_lpc2 = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -384,7 +384,7 @@ struct device_operations mcp55_lpc3 = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -397,7 +397,7 @@ struct device_operations mcp55_lpc4 = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -410,7 +410,7 @@ struct device_operations mcp55_lpc5 = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -423,7 +423,7 @@ struct device_operations mcp55_lpc6 = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -436,7 +436,7 @@ struct device_operations mcp55_lpcslave = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = lpc_slave_init,
.ops_pci = &mcp55_pci_dev_ops_pci,

2
southbridge/nvidia/mcp55/mcp55.c
View file

@ -267,7 +267,7 @@ struct device_operations nvidia_ops = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_enable,
.phase6_init = NULL,
};

2
southbridge/nvidia/mcp55/pci.c
View file

@ -96,7 +96,7 @@ struct device_operations mcp55_pci = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &mcp55_pci_dev_ops_pci,

10
southbridge/nvidia/mcp55/pcie.c
View file

@ -54,7 +54,7 @@ struct device_operations mcp55_pcie_a = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -68,7 +68,7 @@ struct device_operations mcp55_pcie_b_c = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -82,7 +82,7 @@ struct device_operations mcp55_pcie_d = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -96,7 +96,7 @@ struct device_operations mcp55_pcie_e = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@ -110,7 +110,7 @@ struct device_operations mcp55_pcie_f = {
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,

2
southbridge/nvidia/mcp55/sata.c
View file

@ -76,7 +76,7 @@ struct device_operations mcp55_sata = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
.ops_pci = &mcp55_pci_dev_ops_pci,

2
southbridge/nvidia/mcp55/smbus.c
View file

@ -136,7 +136,7 @@ struct device_operations mcp55_smbus = {
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_sm_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = mcp55_sm_init,
.ops_pci = &mcp55_pci_dev_ops_pci,

2
southbridge/nvidia/mcp55/usb.c
View file

@ -43,7 +43,7 @@ struct device_operations mcp55_usb = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &mcp55_pci_dev_ops_pci,

2
southbridge/nvidia/mcp55/usb2.c
View file

@ -56,7 +56,7 @@ static void usb2_set_resources(struct device *dev)
old_debug = get_ehci_debug();
set_ehci_debug(0);
#endif
pci_dev_set_resources(dev);
pci_set_resources(dev);
#ifdef CONFIG_USBDEBUG_DIRECT
res = find_resource(dev, 0x10);

2
southbridge/via/vt8237/ide.c
View file

@ -99,7 +99,7 @@ struct device_operations vt8237_ide = {
.phase3_scan = 0,
//.phase4_enable_disable = vt8237_enable,
//.phase4_read_resources = pci_dev_read_resources,
//.phase4_set_resources = pci_dev_set_resources,
//.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
};

4
southbridge/via/vt8237/lpc.c
View file

@ -451,7 +451,7 @@ struct device_operations vt8237r_lpc = {
.phase2_fixup = vt8237_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = vt8237_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = vt8237_enable_resources,
.phase6_init = vt8237r_init,
};
@ -464,7 +464,7 @@ struct device_operations vt8237s_lpc = {
.phase2_fixup = vt8237_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = vt8237_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = vt8237_enable_resources,
.phase6_init = vt8237s_init,
};

4
southbridge/via/vt8237/sata.c
View file

@ -103,7 +103,7 @@ struct device_operations vt8237r_sata = {
.phase3_scan = 0,
//.phase4_enable_disable = vt8237_enable,
//.phase4_read_resources = pci_dev_read_resources,
//.phase4_set_resources = pci_dev_set_resources,
//.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_i_init,
};
@ -117,7 +117,7 @@ struct device_operations vt8237s_sata = {
.phase3_scan = 0,
//.phase4_enable_disable = vt8237_enable,
//.phase4_read_resources = pci_dev_read_resources,
//.phase4_set_resources = pci_dev_set_resources,
//.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_ii_init,
};