diff --git a/device/agp_device.c b/device/agp_device.c index c316aac197..b7dbad359f 100644 --- a/device/agp_device.c +++ b/device/agp_device.c @@ -61,7 +61,7 @@ static const struct pci_operations agp_bus_ops_pci = { const struct device_operations default_agp_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_set_resources, .enable_resources = pci_bus_enable_resources, .init = 0, .scan_bus = agp_scan_bridge, diff --git a/device/cardbus_device.c b/device/cardbus_device.c index 3c73a2455b..9fc7657d20 100644 --- a/device/cardbus_device.c +++ b/device/cardbus_device.c @@ -244,7 +244,7 @@ unsigned int cardbus_scan_bridge(struct device *dev, unsigned int max) const struct device_operations default_cardbus_ops_bus = { .phase3_scan = cardbus_scan_bridge, .phase4_read_resources = cardbus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = cardbus_enable_resources, .phase6_init = 0, .reset_bus = pci_bus_reset, diff --git a/device/hypertransport.c b/device/hypertransport.c index 64bfe6419e..6193eb4947 100644 --- a/device/hypertransport.c +++ b/device/hypertransport.c @@ -638,7 +638,7 @@ static const struct pci_operations ht_bus_ops_pci = { const struct device_operations default_ht_ops_bus = { .phase3_scan = ht_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = 0, .reset_bus = pci_bus_reset, diff --git a/device/pci_device.c b/device/pci_device.c index f07833e0cf..1dbba433e3 100644 --- a/device/pci_device.c +++ b/device/pci_device.c @@ -567,7 +567,7 @@ static void pci_set_resource(struct device *dev, struct resource *resource) return; } -void pci_dev_set_resources(struct device *dev) +void pci_set_resources(struct device *dev) { struct resource *resource, *last; unsigned int link; @@ -742,7 +742,7 @@ const struct pci_operations pci_dev_ops_pci = { const struct device_operations default_pci_ops_dev = { .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = pci_dev_init, .phase3_scan = 0, @@ -757,7 +757,7 @@ const struct pci_operations pci_bus_ops_pci = { const struct device_operations default_pci_ops_bus = { .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = 0, .reset_bus = pci_bus_reset, diff --git a/device/pcie_device.c b/device/pcie_device.c index 5cd59cc918..9660b95f8b 100644 --- a/device/pcie_device.c +++ b/device/pcie_device.c @@ -64,7 +64,7 @@ static const struct pci_operations pcie_bus_ops_pci = { const struct device_operations default_pcie_ops_bus = { .phase3_scan = pcie_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = 0, .reset_bus = pci_bus_reset, diff --git a/device/pcix_device.c b/device/pcix_device.c index fd84f2f29c..63a4849d03 100644 --- a/device/pcix_device.c +++ b/device/pcix_device.c @@ -142,7 +142,7 @@ struct pci_operations pcix_bus_ops_pci = { struct device_operations default_pcix_ops_bus = { .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = 0, .phase3_scan = pcix_scan_bridge, diff --git a/include/device/pci.h b/include/device/pci.h index f4abbcf38d..ca1b6cd7e4 100644 --- a/include/device/pci.h +++ b/include/device/pci.h @@ -78,7 +78,7 @@ extern const struct pci_operations pci_bus_ops_pci; void pci_dev_read_resources(struct device * dev); void pci_bus_read_resources(struct device * dev); -void pci_dev_set_resources(struct device * dev); +void pci_set_resources(struct device * dev); void pci_dev_enable_resources(struct device * dev); void pci_bus_enable_resources(struct device * dev); void pci_bus_reset(struct bus *bus); diff --git a/mainboard/emulation/qemu-x86/vga.c b/mainboard/emulation/qemu-x86/vga.c index 4892d69a7c..037a0d9d4f 100644 --- a/mainboard/emulation/qemu-x86/vga.c +++ b/mainboard/emulation/qemu-x86/vga.c @@ -53,7 +53,7 @@ struct device_operations qemuvga_pci_ops_dev = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = setup_onboard, .ops_pci = &pci_dev_ops_pci, diff --git a/mainboard/kontron/986lcd-m/rtl8168.c b/mainboard/kontron/986lcd-m/rtl8168.c index 064666c6b9..98105289a3 100644 --- a/mainboard/kontron/986lcd-m/rtl8168.c +++ b/mainboard/kontron/986lcd-m/rtl8168.c @@ -43,7 +43,7 @@ struct device_operations nic_ops = { .device = 0x8168}}}, .constructor = default_device_constructor, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = nic_init, .ops_pci = &pci_dev_ops_pci, diff --git a/northbridge/intel/i945/northbridge.c b/northbridge/intel/i945/northbridge.c index 15917416ca..9c7098842d 100644 --- a/northbridge/intel/i945/northbridge.c +++ b/northbridge/intel/i945/northbridge.c @@ -197,6 +197,7 @@ static void mc_read_resources(struct device * dev) pci_dev_read_resources(dev); +#warning After we fix the allocator we need to fix this! /* So, this is one of the big mysteries in the coreboot resource * allocator. This resource should make sure that the address space * of the PCIe memory mapped config space bar. But it does not. @@ -226,7 +227,7 @@ static void mc_set_resources(struct device * dev) } /* And call the normal set_resources */ - pci_dev_set_resources(dev); + pci_set_resources(dev); } static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) diff --git a/northbridge/via/cn700/agp.c b/northbridge/via/cn700/agp.c index 30aa9d6719..3d7a3c848d 100644 --- a/northbridge/via/cn700/agp.c +++ b/northbridge/via/cn700/agp.c @@ -108,7 +108,7 @@ struct device_operations cn700_agp = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_dev_set_resources, + //.phase4_set_resources = pci_set_resources, //.phase5_enable_resources = pci_dev_enable_resources, .phase6_init = agp_init, }; diff --git a/northbridge/via/cn700/pci.c b/northbridge/via/cn700/pci.c index 33fdc72756..3f8f2cefc8 100644 --- a/northbridge/via/cn700/pci.c +++ b/northbridge/via/cn700/pci.c @@ -55,7 +55,7 @@ struct device_operations cn700_pci_bridge = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_dev_set_resources, + //.phase4_set_resources = pci_set_resources, //.phase5_enable_resources = pci_dev_enable_resources, .phase6_init = pci_bridge_init, }; diff --git a/northbridge/via/cn700/vga.c b/northbridge/via/cn700/vga.c index 85dfef6c1a..c8965b0136 100644 --- a/northbridge/via/cn700/vga.c +++ b/northbridge/via/cn700/vga.c @@ -73,7 +73,7 @@ struct device_operations cn700_vga = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = vga_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = vga_init, }; diff --git a/southbridge/amd/amd8111/ac97.c b/southbridge/amd/amd8111/ac97.c index 6428738a59..abe9ad14d1 100644 --- a/southbridge/amd/amd8111/ac97.c +++ b/southbridge/amd/amd8111/ac97.c @@ -46,7 +46,7 @@ struct device_operations ac97audio = { .phase3_scan = 0, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &lops_pci, @@ -60,7 +60,7 @@ struct device_operations ac97modem = { .phase3_scan = 0, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &lops_pci, diff --git a/southbridge/amd/amd8111/acpi.c b/southbridge/amd/amd8111/acpi.c index 60bba0f6b5..40462a062a 100644 --- a/southbridge/amd/amd8111/acpi.c +++ b/southbridge/amd/amd8111/acpi.c @@ -233,7 +233,7 @@ struct device_operations acpi = { .phase3_scan = scan_static_bus, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = acpi_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = acpi_enable_resources, .phase6_init = acpi_init, .ops_pci = &lops_pci, diff --git a/southbridge/amd/amd8111/ide.c b/southbridge/amd/amd8111/ide.c index e8eba1a596..6f4a16d58f 100644 --- a/southbridge/amd/amd8111/ide.c +++ b/southbridge/amd/amd8111/ide.c @@ -80,7 +80,7 @@ struct device_operations amd8111_ide = { .phase3_scan = 0, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, .ops_pci = &lops_pci diff --git a/southbridge/amd/amd8111/lpc.c b/southbridge/amd/amd8111/lpc.c index 6192d6781f..299f8e6af9 100644 --- a/southbridge/amd/amd8111/lpc.c +++ b/southbridge/amd/amd8111/lpc.c @@ -215,7 +215,7 @@ struct device_operations amd8111_lpc = { .phase3_scan = scan_static_bus, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = amd8111_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = amd8111_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &lops_pci, diff --git a/southbridge/amd/amd8111/nic.c b/southbridge/amd/amd8111/nic.c index efbca51d3e..1101a6cc29 100644 --- a/southbridge/amd/amd8111/nic.c +++ b/southbridge/amd/amd8111/nic.c @@ -101,7 +101,7 @@ struct device_operations amd8111_nic = { .phase3_scan = 0, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = nic_init, .ops_pci = &lops_pci, diff --git a/southbridge/amd/amd8111/pci.c b/southbridge/amd/amd8111/pci.c index 30eef5a4f0..a200b3a321 100644 --- a/southbridge/amd/amd8111/pci.c +++ b/southbridge/amd/amd8111/pci.c @@ -77,7 +77,7 @@ struct device_operations amd8111_pci = { .phase3_scan = pci_scan_bridge, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, }; diff --git a/southbridge/amd/amd8111/smbus.c b/southbridge/amd/amd8111/smbus.c index 9b6aeb0c55..7a589f21f7 100644 --- a/southbridge/amd/amd8111/smbus.c +++ b/southbridge/amd/amd8111/smbus.c @@ -55,7 +55,7 @@ struct device_operations amd8111_smbus = { .phase3_scan = scan_static_bus, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &lops_pci, diff --git a/southbridge/amd/amd8111/usb.c b/southbridge/amd/amd8111/usb.c index 0534d6cc7b..271377dfcb 100644 --- a/southbridge/amd/amd8111/usb.c +++ b/southbridge/amd/amd8111/usb.c @@ -52,7 +52,7 @@ struct device_operations amd8111_usb = { .phase3_scan = scan_static_bus, .phase3_chip_setup_dev = amd8111_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &lops_pci diff --git a/southbridge/amd/amd8111/usb2.c b/southbridge/amd/amd8111/usb2.c index de8444c447..2942e9c1e4 100644 --- a/southbridge/amd/amd8111/usb2.c +++ b/southbridge/amd/amd8111/usb2.c @@ -51,7 +51,7 @@ struct device_operations amd8111_usb2 = { .phase3_scan = scan_static_bus, .phase3_chip_setup_dev = amd8111_usb2_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, }; diff --git a/southbridge/amd/amd8132/amd8132_bridge.c b/southbridge/amd/amd8132/amd8132_bridge.c index b2d849ec23..62e393f506 100644 --- a/southbridge/amd/amd8132/amd8132_bridge.c +++ b/southbridge/amd/amd8132/amd8132_bridge.c @@ -340,7 +340,7 @@ static void bridge_set_resources(struct device *dev) report_resource_stored(dev, res, "including NPUML"); } - pci_dev_set_resources(dev); + pci_set_resources(dev); } struct device_operations amd8132_pcix = { @@ -420,7 +420,7 @@ struct device_operations amd8132_apic = { .phase3_scan = 0, .phase3_chip_setup_dev = ioapic_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = amd8132_ioapic_init, .ops_pci = &pci_ops_pci_dev, diff --git a/southbridge/amd/amd8151/amd8151_agp3.c b/southbridge/amd/amd8151/amd8151_agp3.c index ece5b5481c..799c3c0008 100644 --- a/southbridge/amd/amd8151/amd8151_agp3.c +++ b/southbridge/amd/amd8151/amd8151_agp3.c @@ -47,7 +47,7 @@ struct device_operations amd8151_agp3bridge = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = agp3bridge_init, }; @@ -82,7 +82,7 @@ struct device_operations amd8151_agp3dev = { .constructor = default_device_constructor, .phase4_enable_disable = agp3dev_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index a4a7327d31..7f55df9e49 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -696,7 +696,7 @@ struct device_operations cs5536_ops = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = cs5536_pci_dev_enable_resources, .phase6_init = southbridge_init, }; @@ -709,7 +709,7 @@ struct device_operations cs5536_ide = { #warning FIXME: what has to go in phase3_scan? .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/amd/rs690/gfx.c b/southbridge/amd/rs690/gfx.c index 586f272a48..06d916b390 100644 --- a/southbridge/amd/rs690/gfx.c +++ b/southbridge/amd/rs690/gfx.c @@ -109,8 +109,9 @@ static void internal_gfx_pci_dev_init(struct device *dev) static void rs690_gfx_set_resources(struct device *dev) { +#warning This does nothing. Implement it or remove it. printk(BIOS_INFO, "rs690_gfx_set_resources.\n"); - pci_dev_set_resources(dev); + pci_set_resources(dev); } /* diff --git a/southbridge/amd/rs690/ht.c b/southbridge/amd/rs690/ht.c index 06344ae20c..23f0468687 100644 --- a/southbridge/amd/rs690/ht.c +++ b/southbridge/amd/rs690/ht.c @@ -88,7 +88,7 @@ struct device_operations rs690_ht = { .phase3_scan = 0, .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, diff --git a/southbridge/amd/rs690/pcie.c b/southbridge/amd/rs690/pcie.c index a45add841d..799a4ab20e 100644 --- a/southbridge/amd/rs690/pcie.c +++ b/southbridge/amd/rs690/pcie.c @@ -402,7 +402,7 @@ struct device_operations rs690_pcie = { .phase3_scan = pci_scan_bridge, .phase3_chip_setup_dev = rs690_enable, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, @@ -416,7 +416,7 @@ struct device_operations rs690_pcie2 = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, @@ -429,7 +429,7 @@ struct device_operations rs690_pcie3 = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, @@ -442,7 +442,7 @@ struct device_operations rs690_pcie4 = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, @@ -455,7 +455,7 @@ struct device_operations rs690_pcie5 = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, @@ -468,7 +468,7 @@ struct device_operations rs690_pcie6 = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, @@ -481,7 +481,7 @@ struct device_operations rs690_pcie7 = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, @@ -494,7 +494,7 @@ struct device_operations rs690_pcie8 = { .constructor = default_device_constructor, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &lops_pci, diff --git a/southbridge/amd/sb600/ac97.c b/southbridge/amd/sb600/ac97.c index bd8aafaf92..58bb5567f1 100644 --- a/southbridge/amd/sb600/ac97.c +++ b/southbridge/amd/sb600/ac97.c @@ -40,7 +40,7 @@ struct device_operations ac97audio = { .phase3_scan = 0, .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &lops_pci, @@ -54,7 +54,7 @@ struct device_operations ac97modem = { .phase3_scan = 0, .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = NULL, .ops_pci = &lops_pci, diff --git a/southbridge/amd/sb600/hda.c b/southbridge/amd/sb600/hda.c index b35c2bb4d9..5b9333a3b6 100644 --- a/southbridge/amd/sb600/hda.c +++ b/southbridge/amd/sb600/hda.c @@ -281,7 +281,7 @@ struct device_operations sb600_hda = { .constructor = default_device_constructor, .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = hda_init, .ops_pci = &lops_pci diff --git a/southbridge/amd/sb600/ide.c b/southbridge/amd/sb600/ide.c index 75d7bd10f7..9e00741c6d 100644 --- a/southbridge/amd/sb600/ide.c +++ b/southbridge/amd/sb600/ide.c @@ -72,7 +72,7 @@ struct device_operations sb600_ide = { .constructor = default_device_constructor, .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, .ops_pci = &lops_pci diff --git a/southbridge/amd/sb600/lpc.c b/southbridge/amd/sb600/lpc.c index 66cbac5692..fd7651c0e4 100644 --- a/southbridge/amd/sb600/lpc.c +++ b/southbridge/amd/sb600/lpc.c @@ -215,7 +215,7 @@ struct device_operations sb600_lpc = { .phase3_scan = scan_static_bus, .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = sb600_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = sb600_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &lops_pci diff --git a/southbridge/amd/sb600/pci.c b/southbridge/amd/sb600/pci.c index 13d48d046d..c80b0ce4da 100644 --- a/southbridge/amd/sb600/pci.c +++ b/southbridge/amd/sb600/pci.c @@ -132,7 +132,7 @@ struct device_operations sb600_pci = { .phase3_scan = pci_scan_bridge, .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .reset_bus = pci_bus_reset, diff --git a/southbridge/amd/sb600/sata.c b/southbridge/amd/sb600/sata.c index f5da26e2fc..bdaf982054 100644 --- a/southbridge/amd/sb600/sata.c +++ b/southbridge/amd/sb600/sata.c @@ -194,7 +194,7 @@ struct device_operations sb600_sata = { .constructor = default_device_constructor, .phase3_chip_setup_dev = sb600_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, .ops_pci = &lops_pci diff --git a/southbridge/amd/sb600/sm.c b/southbridge/amd/sb600/sm.c index 4eacd7540f..909ff56433 100644 --- a/southbridge/amd/sb600/sm.c +++ b/southbridge/amd/sb600/sm.c @@ -376,11 +376,12 @@ static void sb600_sm_read_resources(struct device * dev) compact_resources(dev); } + static void sb600_sm_set_resources(struct device *dev) { struct resource *res; - pci_dev_set_resources(dev); + pci_set_resources(dev); res = find_resource(dev, 0x74); pci_write_config32(dev, 0x74, res->base | 1 << 3); diff --git a/southbridge/amd/sb600/usb.c b/southbridge/amd/sb600/usb.c index 6eb53afb29..f5c00f7a82 100644 --- a/southbridge/amd/sb600/usb.c +++ b/southbridge/amd/sb600/usb.c @@ -143,7 +143,7 @@ static void usb_set_resources(struct device *dev) old_debug = get_ehci_debug(); set_ehci_debug(0); #endif - pci_dev_set_resources(dev); + pci_set_resources(dev); #ifdef CONFIG_USBDEBUG_DIRECT res = find_resource(dev, 0x10); diff --git a/southbridge/intel/i82371eb/i82371eb.c b/southbridge/intel/i82371eb/i82371eb.c index f9cdecb75b..62e1949d17 100644 --- a/southbridge/intel/i82371eb/i82371eb.c +++ b/southbridge/intel/i82371eb/i82371eb.c @@ -93,7 +93,7 @@ struct device_operations i82371eb_isa = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_isa_init, .ops_pci = &pci_dev_ops_pci, @@ -105,7 +105,7 @@ struct device_operations i82371eb_ide = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_ide_init, .ops_pci = &pci_dev_ops_pci, @@ -117,7 +117,7 @@ struct device_operations i82371eb_acpi = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = i82371eb_acpi_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/intel/i82801gx/ac97.c b/southbridge/intel/i82801gx/ac97.c index a479a309c9..bd1ccee449 100644 --- a/southbridge/intel/i82801gx/ac97.c +++ b/southbridge/intel/i82801gx/ac97.c @@ -49,7 +49,7 @@ struct device_operations ac97audio = { .phase3_chip_setup_dev = i82801gx_enable, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ac97_audio_init, .ops_pci = &pci_dev_ops_pci, @@ -65,7 +65,7 @@ struct device_operations ac97modem = { .phase3_chip_setup_dev = i82801gx_enable, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ac97_modem_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/intel/i82801gx/ide.c b/southbridge/intel/i82801gx/ide.c index 82c6177aa2..bda4c7de44 100644 --- a/southbridge/intel/i82801gx/ide.c +++ b/southbridge/intel/i82801gx/ide.c @@ -97,7 +97,7 @@ struct device_operations i82801gx_ide = { .phase3_chip_setup_dev = i82801gx_enable, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = ide_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/intel/i82801gx/lpc.c b/southbridge/intel/i82801gx/lpc.c index 54ec795a0d..ba36107846 100644 --- a/southbridge/intel/i82801gx/lpc.c +++ b/southbridge/intel/i82801gx/lpc.c @@ -343,7 +343,7 @@ struct device_operations ich7_ich7r_ich7dh_lpc = { .phase3_chip_setup_dev = i82801gx_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = i82801gx_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = i82801gx_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &pci_ops, @@ -360,7 +360,7 @@ struct device_operations ich7m_ich7u_lpc = { .phase3_chip_setup_dev = i82801gx_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = i82801gx_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = i82801gx_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &pci_ops, @@ -376,7 +376,7 @@ struct device_operations ich7m_dh_lpc = { .phase3_chip_setup_dev = i82801gx_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = i82801gx_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = i82801gx_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &pci_ops, diff --git a/southbridge/intel/i82801gx/nic.c b/southbridge/intel/i82801gx/nic.c index 76a800dcb9..ebef4d64c8 100644 --- a/southbridge/intel/i82801gx/nic.c +++ b/southbridge/intel/i82801gx/nic.c @@ -44,7 +44,7 @@ struct device_operations i82801gx_nic= { .device = 0x27dc}}}, .constructor = default_device_constructor, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = nic_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/intel/i82801gx/pci.c b/southbridge/intel/i82801gx/pci.c index b0f9f7e36c..d1dc232e16 100644 --- a/southbridge/intel/i82801gx/pci.c +++ b/southbridge/intel/i82801gx/pci.c @@ -132,7 +132,7 @@ struct device_operations i82801g_pci = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = ich_pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, @@ -148,7 +148,7 @@ struct device_operations i82801gmu_pci = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = ich_pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/intel/i82801gx/pcie.c b/southbridge/intel/i82801gx/pcie.c index c8cac9902e..1e592e15ce 100644 --- a/southbridge/intel/i82801gx/pcie.c +++ b/southbridge/intel/i82801gx/pcie.c @@ -89,7 +89,7 @@ struct device_operations i82801gx_pcie_port1 = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, @@ -104,7 +104,7 @@ struct device_operations i82801gx_pcie_port2 = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, @@ -119,7 +119,7 @@ struct device_operations i82801gx_pcie_port3 = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, @@ -134,7 +134,7 @@ struct device_operations i82801gx_pcie_port4 = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, @@ -149,7 +149,7 @@ struct device_operations i82801gx_pcie_port5 = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, @@ -164,7 +164,7 @@ struct device_operations i82801gx_pcie_port6 = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_bus_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/intel/i82801gx/sata.c b/southbridge/intel/i82801gx/sata.c index 2663a2de37..c049b22643 100644 --- a/southbridge/intel/i82801gx/sata.c +++ b/southbridge/intel/i82801gx/sata.c @@ -150,7 +150,7 @@ struct device_operations i82801gx_sata_normal_driver = { .reset_bus = pci_bus_reset, .phase3_chip_setup_dev = i82801gx_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, .ops_pci = &pci_dev_ops_pci, @@ -198,4 +198,4 @@ static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = 0x27c6, }; -#endif \ No newline at end of file +#endif diff --git a/southbridge/intel/i82801gx/smbus.c b/southbridge/intel/i82801gx/smbus.c index 59da31b5c2..aa0b757485 100644 --- a/southbridge/intel/i82801gx/smbus.c +++ b/southbridge/intel/i82801gx/smbus.c @@ -56,7 +56,7 @@ struct device_operations i82801gx_smbus = { .phase3_chip_setup_dev = i82801gx_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/southbridge/intel/i82801gx/usb.c b/southbridge/intel/i82801gx/usb.c index c66be1852a..b06c0b1532 100644 --- a/southbridge/intel/i82801gx/usb.c +++ b/southbridge/intel/i82801gx/usb.c @@ -56,7 +56,7 @@ struct device_operations i82801gb_usb1 = { .constructor = default_device_constructor, .phase3_chip_setup_dev = i82801gx_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, .ops_pci = &pci_dev_ops_pci, @@ -70,7 +70,7 @@ struct device_operations i82801gb_usb2 = { .constructor = default_device_constructor, .phase3_chip_setup_dev = i82801gx_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, .ops_pci = &pci_dev_ops_pci, @@ -84,7 +84,7 @@ struct device_operations i82801gb_usb3 = { .constructor = default_device_constructor, .phase3_chip_setup_dev = i82801gx_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, .ops_pci = &pci_dev_ops_pci, @@ -98,7 +98,7 @@ struct device_operations i82801gb_usb4 = { .constructor = default_device_constructor, .phase3_chip_setup_dev = i82801gx_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, .ops_pci = &pci_dev_ops_pci, diff --git a/southbridge/intel/i82801gx/usb_ehci.c b/southbridge/intel/i82801gx/usb_ehci.c index c531bf19fe..0fb30856bf 100644 --- a/southbridge/intel/i82801gx/usb_ehci.c +++ b/southbridge/intel/i82801gx/usb_ehci.c @@ -80,7 +80,7 @@ struct device_operations i82801gx_usb_ehci = { .constructor = default_device_constructor, .phase3_chip_setup_dev = i82801gx_enable, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = usb_ehci_init, .ops_pci = &lops_pci, diff --git a/southbridge/nvidia/mcp55/ide.c b/southbridge/nvidia/mcp55/ide.c index 34a83f8689..ce84e1a42e 100644 --- a/southbridge/nvidia/mcp55/ide.c +++ b/southbridge/nvidia/mcp55/ide.c @@ -77,7 +77,7 @@ struct device_operations mcp55_ide = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, .ops_pci = &mcp55_pci_dev_ops_pci, diff --git a/southbridge/nvidia/mcp55/lpc.c b/southbridge/nvidia/mcp55/lpc.c index 1d0c9b46ef..8a33ad9ab9 100644 --- a/southbridge/nvidia/mcp55/lpc.c +++ b/southbridge/nvidia/mcp55/lpc.c @@ -345,7 +345,7 @@ struct device_operations mcp55_lpc = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -358,7 +358,7 @@ struct device_operations mcp55_pro = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -371,7 +371,7 @@ struct device_operations mcp55_lpc2 = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -384,7 +384,7 @@ struct device_operations mcp55_lpc3 = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -397,7 +397,7 @@ struct device_operations mcp55_lpc4 = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -410,7 +410,7 @@ struct device_operations mcp55_lpc5 = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -423,7 +423,7 @@ struct device_operations mcp55_lpc6 = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -436,7 +436,7 @@ struct device_operations mcp55_lpcslave = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_lpc_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = lpc_slave_init, .ops_pci = &mcp55_pci_dev_ops_pci, diff --git a/southbridge/nvidia/mcp55/mcp55.c b/southbridge/nvidia/mcp55/mcp55.c index fc930b74b4..e57aa24b65 100644 --- a/southbridge/nvidia/mcp55/mcp55.c +++ b/southbridge/nvidia/mcp55/mcp55.c @@ -267,7 +267,7 @@ struct device_operations nvidia_ops = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = mcp55_enable, .phase6_init = NULL, }; diff --git a/southbridge/nvidia/mcp55/pci.c b/southbridge/nvidia/mcp55/pci.c index 057bf2d9c7..0a868240be 100644 --- a/southbridge/nvidia/mcp55/pci.c +++ b/southbridge/nvidia/mcp55/pci.c @@ -96,7 +96,7 @@ struct device_operations mcp55_pci = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, .ops_pci = &mcp55_pci_dev_ops_pci, diff --git a/southbridge/nvidia/mcp55/pcie.c b/southbridge/nvidia/mcp55/pcie.c index e3ad45c65e..7b5e402e98 100644 --- a/southbridge/nvidia/mcp55/pcie.c +++ b/southbridge/nvidia/mcp55/pcie.c @@ -54,7 +54,7 @@ struct device_operations mcp55_pcie_a = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -68,7 +68,7 @@ struct device_operations mcp55_pcie_b_c = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -82,7 +82,7 @@ struct device_operations mcp55_pcie_d = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -96,7 +96,7 @@ struct device_operations mcp55_pcie_e = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &mcp55_pci_dev_ops_pci, @@ -110,7 +110,7 @@ struct device_operations mcp55_pcie_f = { .reset_bus = pci_bus_reset, .phase3_scan = pci_scan_bridge, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, .ops_pci = &mcp55_pci_dev_ops_pci, diff --git a/southbridge/nvidia/mcp55/sata.c b/southbridge/nvidia/mcp55/sata.c index 1df2169ed9..43204bd9d2 100644 --- a/southbridge/nvidia/mcp55/sata.c +++ b/southbridge/nvidia/mcp55/sata.c @@ -76,7 +76,7 @@ struct device_operations mcp55_sata = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, .ops_pci = &mcp55_pci_dev_ops_pci, diff --git a/southbridge/nvidia/mcp55/smbus.c b/southbridge/nvidia/mcp55/smbus.c index a83df66572..25da1e53e5 100644 --- a/southbridge/nvidia/mcp55/smbus.c +++ b/southbridge/nvidia/mcp55/smbus.c @@ -136,7 +136,7 @@ struct device_operations mcp55_smbus = { .constructor = default_device_constructor, .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_sm_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = mcp55_sm_init, .ops_pci = &mcp55_pci_dev_ops_pci, diff --git a/southbridge/nvidia/mcp55/usb.c b/southbridge/nvidia/mcp55/usb.c index 7b5c1705fc..2d32836198 100644 --- a/southbridge/nvidia/mcp55/usb.c +++ b/southbridge/nvidia/mcp55/usb.c @@ -43,7 +43,7 @@ struct device_operations mcp55_usb = { .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, .ops_pci = &mcp55_pci_dev_ops_pci, diff --git a/southbridge/nvidia/mcp55/usb2.c b/southbridge/nvidia/mcp55/usb2.c index 6ba3c103e7..48fb300275 100644 --- a/southbridge/nvidia/mcp55/usb2.c +++ b/southbridge/nvidia/mcp55/usb2.c @@ -56,7 +56,7 @@ static void usb2_set_resources(struct device *dev) old_debug = get_ehci_debug(); set_ehci_debug(0); #endif - pci_dev_set_resources(dev); + pci_set_resources(dev); #ifdef CONFIG_USBDEBUG_DIRECT res = find_resource(dev, 0x10); diff --git a/southbridge/via/vt8237/ide.c b/southbridge/via/vt8237/ide.c index 9fdac4d213..5caeb862c1 100644 --- a/southbridge/via/vt8237/ide.c +++ b/southbridge/via/vt8237/ide.c @@ -99,7 +99,7 @@ struct device_operations vt8237_ide = { .phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, //.phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_dev_set_resources, + //.phase4_set_resources = pci_set_resources, //.phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, }; diff --git a/southbridge/via/vt8237/lpc.c b/southbridge/via/vt8237/lpc.c index 64592c55c9..0fc2b9637d 100644 --- a/southbridge/via/vt8237/lpc.c +++ b/southbridge/via/vt8237/lpc.c @@ -451,7 +451,7 @@ struct device_operations vt8237r_lpc = { .phase2_fixup = vt8237_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = vt8237_enable_resources, .phase6_init = vt8237r_init, }; @@ -464,7 +464,7 @@ struct device_operations vt8237s_lpc = { .phase2_fixup = vt8237_enable, .phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, - .phase4_set_resources = pci_dev_set_resources, + .phase4_set_resources = pci_set_resources, .phase5_enable_resources = vt8237_enable_resources, .phase6_init = vt8237s_init, }; diff --git a/southbridge/via/vt8237/sata.c b/southbridge/via/vt8237/sata.c index aaf4490176..aa976c0338 100644 --- a/southbridge/via/vt8237/sata.c +++ b/southbridge/via/vt8237/sata.c @@ -103,7 +103,7 @@ struct device_operations vt8237r_sata = { .phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, //.phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_dev_set_resources, + //.phase4_set_resources = pci_set_resources, //.phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_i_init, }; @@ -117,7 +117,7 @@ struct device_operations vt8237s_sata = { .phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, //.phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_dev_set_resources, + //.phase4_set_resources = pci_set_resources, //.phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_ii_init, };