From 713f809952a2d8da434d619d48cb7ddce1991925 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 17 Jul 2014 11:31:57 -0700 Subject: [PATCH] baytrail: there is a chance that USBPHY_COMPBG is set to 0 Due to some projects don't have the correct settings in devicetree.cb so put this change in case those projects without are setting in devicetree.cb BUG=chrome-os-partner:30690 BRANCH=none TEST=emerge-rambi coreboot without problem checked the USBPHY_COMPBG is configured properly even there is no setting in devicetree Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6 Signed-off-by: Kane Chen Reviewed-on: https://chromium-review.googlesource.com/209051 Reviewed-by: Shawn Nematbakhsh --- src/soc/intel/baytrail/ehci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index c1d5a1e5f2..d5bd45f8bb 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -94,10 +94,12 @@ static const struct reg_script ehci_hc_reset[] = { static void usb2_phy_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; + u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ? + 0x4700 : config->usb2_comp_bg); struct reg_script usb2_phy_script[] = { /* USB3PHYInit() */ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, - config->usb2_comp_bg), + usb2_comp_bg), /* Per port phy settings, set in devicetree.cb */ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, config->usb2_per_port_lane0),