From 6df02490a709c3cd49dce5e0bce4a36bb24ce2ef Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Fri, 28 Feb 2025 17:07:05 +0530 Subject: [PATCH] mb/google/brya/vell: Enable RTD3 for SSD to resolve S0ix issue Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on vell and verify that the device suspends to S0ix. Change-Id: I9015f992cc797af013e8882630220b3df41dc9b3 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/86646 Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/mainboard/google/brya/variants/vell/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 697d0ef674..6f9b325a19 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -191,6 +191,13 @@ chip soc/intel/alderlake .clk_src = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D3)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end end device ref tbt_pcie_rp3 on end device ref cnvi_wifi on