Having received no comments on this pro or con, and knowing we have to
have this code, I'm comitting it. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@934 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
8b1b420e6b
commit
6dc3ebfb5c
8 changed files with 279 additions and 11 deletions
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@ -393,6 +393,7 @@ static struct pci_operations lops_pci = {
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.set_subsystem = 0,
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};
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struct device_operations rs690_pcie = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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@ -407,16 +408,94 @@ struct device_operations rs690_pcie = {
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.ops_pci = &lops_pci,
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};
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/* not yet until we figure out how to handle gpp_configuration and port_enable -- are they per port or per chip? Should they
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* be per port or per chip?
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static struct pci_driver pcie_driver_dev7 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7,
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/* the rest of these have no phase4_enable_disable; it is all managed by the above device. */
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struct device_operations rs690_pcie2 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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static struct pci_driver pcie_driver_dev8 __pci_driver = {
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.ops = &pcie_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8,
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struct device_operations rs690_pcie3 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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struct device_operations rs690_pcie4 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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struct device_operations rs690_pcie5 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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struct device_operations rs690_pcie6 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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struct device_operations rs690_pcie7 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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struct device_operations rs690_pcie8 = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pcie_init,
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.ops_pci = &lops_pci,
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};
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*/
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27
southbridge/amd/rs690/pcie2.dts
Normal file
27
southbridge/amd/rs690/pcie2.dts
Normal file
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff0000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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*/
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{
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device_operations = "rs690_pcie2";
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};
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27
southbridge/amd/rs690/pcie3.dts
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27
southbridge/amd/rs690/pcie3.dts
Normal file
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff0000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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*/
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{
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device_operations = "rs690_pcie3";
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};
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27
southbridge/amd/rs690/pcie4.dts
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27
southbridge/amd/rs690/pcie4.dts
Normal file
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff0000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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*/
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{
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device_operations = "rs690_pcie4";
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};
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27
southbridge/amd/rs690/pcie5.dts
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27
southbridge/amd/rs690/pcie5.dts
Normal file
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff0000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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*/
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{
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device_operations = "rs690_pcie5";
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};
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27
southbridge/amd/rs690/pcie6.dts
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27
southbridge/amd/rs690/pcie6.dts
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff0000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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*/
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{
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device_operations = "rs690_pcie6";
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};
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27
southbridge/amd/rs690/pcie7.dts
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27
southbridge/amd/rs690/pcie7.dts
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff0000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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*/
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{
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device_operations = "rs690_pcie7";
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};
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27
southbridge/amd/rs690/pcie8.dts
Normal file
27
southbridge/amd/rs690/pcie8.dts
Normal file
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
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#Define vga_rom_address = 0xfff0000
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#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
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*/
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{
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device_operations = "rs690_pcie8";
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};
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