From 6dc3ebfb5c8e4c2831c6ec4a86cead83ab482855 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 16 Oct 2008 16:02:12 +0000 Subject: [PATCH] Having received no comments on this pro or con, and knowing we have to have this code, I'm comitting it. Signed-off-by: Ronald G. Minnich Acked-by: Ronald G. Minnich git-svn-id: svn://coreboot.org/repository/coreboot-v3@934 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- southbridge/amd/rs690/pcie.c | 101 ++++++++++++++++++++++++++++---- southbridge/amd/rs690/pcie2.dts | 27 +++++++++ southbridge/amd/rs690/pcie3.dts | 27 +++++++++ southbridge/amd/rs690/pcie4.dts | 27 +++++++++ southbridge/amd/rs690/pcie5.dts | 27 +++++++++ southbridge/amd/rs690/pcie6.dts | 27 +++++++++ southbridge/amd/rs690/pcie7.dts | 27 +++++++++ southbridge/amd/rs690/pcie8.dts | 27 +++++++++ 8 files changed, 279 insertions(+), 11 deletions(-) create mode 100644 southbridge/amd/rs690/pcie2.dts create mode 100644 southbridge/amd/rs690/pcie3.dts create mode 100644 southbridge/amd/rs690/pcie4.dts create mode 100644 southbridge/amd/rs690/pcie5.dts create mode 100644 southbridge/amd/rs690/pcie6.dts create mode 100644 southbridge/amd/rs690/pcie7.dts create mode 100644 southbridge/amd/rs690/pcie8.dts diff --git a/southbridge/amd/rs690/pcie.c b/southbridge/amd/rs690/pcie.c index 1f01d284cf..ab64448003 100644 --- a/southbridge/amd/rs690/pcie.c +++ b/southbridge/amd/rs690/pcie.c @@ -393,6 +393,7 @@ static struct pci_operations lops_pci = { .set_subsystem = 0, }; + struct device_operations rs690_pcie = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, @@ -407,16 +408,94 @@ struct device_operations rs690_pcie = { .ops_pci = &lops_pci, }; -/* not yet until we figure out how to handle gpp_configuration and port_enable -- are they per port or per chip? Should they - * be per port or per chip? -static struct pci_driver pcie_driver_dev7 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7, +/* the rest of these have no phase4_enable_disable; it is all managed by the above device. */ +struct device_operations rs690_pcie2 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, }; -static struct pci_driver pcie_driver_dev8 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8, + +struct device_operations rs690_pcie3 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie4 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie5 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie6 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie7 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie8 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, }; -*/ diff --git a/southbridge/amd/rs690/pcie2.dts b/southbridge/amd/rs690/pcie2.dts new file mode 100644 index 0000000000..ecb9260ed2 --- /dev/null +++ b/southbridge/amd/rs690/pcie2.dts @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie2"; +}; diff --git a/southbridge/amd/rs690/pcie3.dts b/southbridge/amd/rs690/pcie3.dts new file mode 100644 index 0000000000..70c505e460 --- /dev/null +++ b/southbridge/amd/rs690/pcie3.dts @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie3"; +}; diff --git a/southbridge/amd/rs690/pcie4.dts b/southbridge/amd/rs690/pcie4.dts new file mode 100644 index 0000000000..d5bbd22b3a --- /dev/null +++ b/southbridge/amd/rs690/pcie4.dts @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie4"; +}; diff --git a/southbridge/amd/rs690/pcie5.dts b/southbridge/amd/rs690/pcie5.dts new file mode 100644 index 0000000000..0768996473 --- /dev/null +++ b/southbridge/amd/rs690/pcie5.dts @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie5"; +}; diff --git a/southbridge/amd/rs690/pcie6.dts b/southbridge/amd/rs690/pcie6.dts new file mode 100644 index 0000000000..041138c4a5 --- /dev/null +++ b/southbridge/amd/rs690/pcie6.dts @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie6"; +}; diff --git a/southbridge/amd/rs690/pcie7.dts b/southbridge/amd/rs690/pcie7.dts new file mode 100644 index 0000000000..49db39b959 --- /dev/null +++ b/southbridge/amd/rs690/pcie7.dts @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie7"; +}; diff --git a/southbridge/amd/rs690/pcie8.dts b/southbridge/amd/rs690/pcie8.dts new file mode 100644 index 0000000000..8ba383f5bc --- /dev/null +++ b/southbridge/amd/rs690/pcie8.dts @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie8"; +};