diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
index e23fc9ad5a..b1b3b9c86e 100644
--- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
@@ -41,6 +41,7 @@ const struct cpu_tdp_power_limits limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_1,
 		.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
 		.pl1_min_power = 19000,
 		.pl1_max_power = 28000,
 		.pl2_min_power = 64000,
@@ -50,6 +51,7 @@ const struct cpu_tdp_power_limits limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_3,
 		.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
 		.pl1_min_power = 19000,
 		.pl1_max_power = 28000,
 		.pl2_min_power = 64000,
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
index 14fbad2462..2b920adf5e 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
+++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
@@ -15,6 +15,7 @@ const struct cpu_tdp_power_limits performance_efficient_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
 		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 15000,
 		.pl2_min_power = 57000,
@@ -24,6 +25,7 @@ const struct cpu_tdp_power_limits performance_efficient_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
 		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 15000,
 		.pl2_min_power = 57000,
@@ -36,6 +38,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
 		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 15000,
 		.pl2_min_power = 57000,
@@ -45,6 +48,7 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
 		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 15000,
 		.pl2_min_power = 57000,
diff --git a/src/mainboard/google/rex/variants/deku/ramstage.c b/src/mainboard/google/rex/variants/deku/ramstage.c
index 0cfcae19f5..871313c319 100644
--- a/src/mainboard/google/rex/variants/deku/ramstage.c
+++ b/src/mainboard/google/rex/variants/deku/ramstage.c
@@ -14,6 +14,7 @@ const struct cpu_tdp_power_limits variant_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_1,
 		.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
 		.pl1_min_power = 19000,
 		.pl1_max_power = 28000,
 		.pl2_min_power = 64000,
@@ -23,6 +24,7 @@ const struct cpu_tdp_power_limits variant_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_3,
 		.cpu_tdp = 28,
+		.power_limits_index = MTL_P_682_482_CORE,
 		.pl1_min_power = 19000,
 		.pl1_max_power = 28000,
 		.pl2_min_power = 64000,
diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c
index edddd43a0a..00ee19f535 100644
--- a/src/mainboard/google/rex/variants/screebo/variant.c
+++ b/src/mainboard/google/rex/variants/screebo/variant.c
@@ -35,6 +35,7 @@ const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
 		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 15000,
 		.pl2_min_power = 40000,
@@ -44,6 +45,7 @@ const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
 		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 15000,
 		.pl2_min_power = 40000,
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
index aee3d888a1..16f85ba6dd 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <chip.h>
 #include <device/pci_ids.h>
 #include <intelblocks/power_limit.h>
 
@@ -13,6 +14,7 @@ const struct cpu_tdp_power_limits limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
 		.cpu_tdp = 15,
+		.power_limits_index = MTL_P_282_242_CORE,
 		.pl1_min_power = 10000,
 		.pl1_max_power = 15000,
 		.pl2_min_power = 57000,
diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h
index 290a3a3659..d02eaa1352 100644
--- a/src/soc/intel/common/block/include/intelblocks/power_limit.h
+++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h
@@ -45,6 +45,7 @@ u8 get_cpu_tdp(void);
 struct cpu_tdp_power_limits {
 	uint16_t mch_id;
 	uint8_t cpu_tdp;
+	uint32_t power_limits_index;
 	unsigned int pl1_min_power;
 	unsigned int pl1_max_power;
 	unsigned int pl2_min_power;
diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c
index 40a0857dcb..b5fbe899aa 100644
--- a/src/soc/intel/common/block/power_limit/power_limit.c
+++ b/src/soc/intel/common/block/power_limit/power_limit.c
@@ -268,7 +268,8 @@ void variant_update_cpu_power_limits(const struct cpu_tdp_power_limits *limits,
 		} else {
 			struct dptf_power_limits *settings = &config->controls.power_limits;
 			config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
+			struct soc_power_limits_config *soc_config =
+				&conf->power_limits_config[limits[index].power_limits_index];
 			settings->pl1.min_power = limits[index].pl1_min_power;
 			settings->pl1.max_power = limits[index].pl1_max_power;
 			settings->pl2.min_power = limits[index].pl2_min_power;