From 6b42f2a196bfd06e31ad41f4bfd6e41b3be001be Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 3 May 2017 11:24:22 -0700 Subject: [PATCH] UPSTREAM: soc/intel/skylake: Enable SATA ports The current implementation is incorrect and is actually disabling the ports. Fixes that. BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that we can boot from SATA SSD. Change-Id: I908c1ab04b6d5fd823a89bf1a1eae3116920e468 Signed-off-by: Patrick Georgi Original-Commit-Id: d44d0280500d4421601a237a392c488338752825 Original-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Original-Signed-off-by: Shelley Chen Original-Reviewed-on: https://review.coreboot.org/19553 Original-Reviewed-by: Furquan Shaikh Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel Reviewed-on: https://chromium-review.googlesource.com/497404 --- src/soc/intel/skylake/sata.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c index c1104364ff..277d6da246 100644 --- a/src/soc/intel/skylake/sata.c +++ b/src/soc/intel/skylake/sata.c @@ -40,14 +40,16 @@ static void *get_ahci_bar(void) static void sata_final(device_t dev) { void *ahcibar = get_ahci_bar(); - u8 port_impl; + u32 port_impl, temp; dev = PCH_DEV_SATA; /* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + 0x0c); - port_impl = ~port_impl & 0x07; + port_impl = read32(ahcibar + 0x0c) & 0x07; /* Port enable */ - pci_write_config8(dev, 0x92, port_impl); + temp = pci_read_config32(dev, 0x92); + temp |= port_impl; + pci_write_config32(dev, 0x92, temp); + } static struct device_operations sata_ops = {