From 6a503fe5a4f623c27ad13faf6c9e5d5458ebd791 Mon Sep 17 00:00:00 2001 From: Kapil Porwal Date: Thu, 24 Apr 2025 21:44:23 +0530 Subject: [PATCH] mb/google/var/uldrenite: Configure GPP_A16 as NF4 GPP_A16 was wrongly configured to NF2 instead of NF4 i.e. ISH_GP5. Reference: Intel doc#648094 BUG=b:410645679 TEST=Check GPIO config in the OS. Change-Id: Ic91ac116513e27992679b0d301afed3bc057bf71 Signed-off-by: Kapil Porwal Reviewed-on: https://review.coreboot.org/c/coreboot/+/87444 Reviewed-by: Eric Lai Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Yuval Peress --- src/mainboard/google/brya/variants/uldrenite/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index 3695ad0d23..d9ace37526 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -35,7 +35,7 @@ static const struct pad_config gpio_table[] = { /* A15 : USB_OC2# ==> NC */ PAD_NC(GPP_A15, NONE), /* A16 : ISH_GP5 */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4), /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT), /* A18 : DDSP_HPDB ==> NC */