diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
new file mode 100644
index 0000000000..c960347cf2
--- /dev/null
+++ b/src/soc/intel/broadwell/memmap.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci.h>
+#include <broadwell/pci_devs.h>
+#include <broadwell/systemagent.h>
+
+static unsigned long get_top_of_ram(void)
+{
+	/*
+	 * Base of TSEG is top of usable DRAM below 4GiB. The register has
+	 * 1 MiB alignement.
+	 */
+	u32 tom = pci_read_config32(SA_DEV_ROOT, TSEG);
+	return (unsigned long) tom & ~((1 << 20) - 1);
+}
+
+void *cbmem_top(void)
+{
+	return (void *)get_top_of_ram();
+}
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 2800a9a53c..e8fade4d74 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -161,18 +161,3 @@ void sdram_initialize(struct pei_data *pei_data)
 	report_memory_config();
 }
 
-void *cbmem_top(void)
-{
-	/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
-	return (void *)get_top_of_ram();
-}
-
-unsigned long get_top_of_ram(void)
-{
-	/*
-	 * Base of TSEG is top of usable DRAM below 4GiB. The register has
-	 * 1 MiB alignement.
-	 */
-	u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
-	return (unsigned long) tom & ~((1 << 20) - 1);
-}
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 6d22d93bd5..2fd1d6ed32 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -421,16 +421,6 @@ static void systemagent_init(struct device *dev)
 	MCHBAR32(0x5500) = 0x00100001;
 }
 
-void *cbmem_top(void)
-{
-	u32 reg;
-
-	/* The top the reserve regions fall just below the TSEG region. */
-	reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
-
-	return (void *)(reg & ~((1 << 20) - 1));
-}
-
 static void systemagent_enable(device_t dev)
 {
 #if CONFIG_HAVE_ACPI_RESUME