From 67e3579d611b59fe463054a93931895d67177242 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 8 Sep 2021 15:39:35 +0200 Subject: [PATCH] sb/intel/lynxpoint: Enable PCIe Relaxed Order Follow Lynx Point PCH reference code version 1.9.1 to enable PCIe Relaxed Order. Change-Id: If7ba4e826adfc8c220ecc68c4a456fbe3cb99667 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57504 Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) Reviewed-by: Benjamin Doron --- src/southbridge/intel/lynxpoint/lpc.c | 9 +++++++++ src/southbridge/intel/lynxpoint/pcie.c | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 93b74233f7..bd6ac0729e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -272,6 +272,15 @@ static void pch_power_options(struct device *dev) reg16 = RCBA16(0x3f02); reg16 &= ~0xf; RCBA16(0x3f02) = reg16; + + /* Enable PCIe Relaxed Order */ + reg32 = RCBA32(0x2314); + reg32 |= 1 << 31 | 1 << 7; + RCBA32(0x2314) = reg32; + + reg16 = RCBA16(0x1114); + reg16 |= 1 << 15 | 1 << 14; + RCBA16(0x1114) = reg16; } static void configure_dmi_pm(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 645ae7e5bb..7aff60895c 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -685,8 +685,13 @@ static void pch_pcie_early(struct device *dev) pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); else pci_update_config32(dev, 0x200, ~0xfffff, 0); + + pci_update_config32(dev, 0x320, ~(3 << 20 | 7 << 6), 1 << 20 | 3 << 6); } + /* Enable PCIe Relaxed Order. */ + pci_or_config32(dev, 0x320, 3 << 23); + /* Read and write back write-once capability registers. */ pci_update_config32(dev, 0x34, ~0, 0); pci_update_config32(dev, 0x40, ~0, 0);