From 661c6baf5cfccfbd331760000787c3d227bb2f22 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Tue, 28 Jan 2025 14:42:33 +0100 Subject: [PATCH] tree: Use true, false for dptf_enable dptf_enable is a boolean, so use true false instead of 0 1. Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/86183 Reviewed-by: Erik van den Bogaert Tested-by: build bot (Jenkins) Reviewed-by: Jakub Czapiga --- src/mainboard/51nb/x210/devicetree.cb | 2 +- src/mainboard/aoostar/wtr_r1/devicetree.cb | 2 +- src/mainboard/asrock/h110m/devicetree.cb | 2 +- src/mainboard/facebook/monolith/devicetree.cb | 2 +- src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb | 2 +- .../google/brya/variants/baseboard/brask/devicetree.cb | 2 +- src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 2 +- .../google/brya/variants/baseboard/hades/devicetree.cb | 2 +- .../google/brya/variants/baseboard/nissa/devicetree.cb | 2 +- src/mainboard/google/brya/variants/orisa/overridetree.cb | 2 +- src/mainboard/google/brya/variants/trulo/overridetree.cb | 2 +- src/mainboard/google/brya/variants/uldrenite/overridetree.cb | 2 +- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 2 +- src/mainboard/google/eve/devicetree.cb | 2 +- src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/glados/devicetree.cb | 2 +- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/atlas/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nami/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nautilus/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/nocturne/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/rammus/devicetree.cb | 2 +- src/mainboard/google/poppy/variants/soraka/devicetree.cb | 2 +- src/mainboard/google/puff/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 +- src/mainboard/google/reef/variants/coral/devicetree.cb | 2 +- src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- src/mainboard/google/reef/variants/sand/devicetree.cb | 2 +- src/mainboard/google/reef/variants/snappy/devicetree.cb | 2 +- src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb | 2 +- .../google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb | 2 +- src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 +- .../google/rex/variants/baseboard/rex/devicetree_pre_prod.cb | 2 +- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 +- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 +- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 +- src/mainboard/intel/adlrvp/devicetree.cb | 2 +- src/mainboard/intel/adlrvp/devicetree_n.cb | 2 +- src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb | 2 +- .../intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 +- src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb | 2 +- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- .../intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 +- src/mainboard/kontron/mal10/variants/mal10/devicetree.cb | 2 +- src/mainboard/libretrend/lt1000/devicetree.cb | 2 +- src/mainboard/protectli/vault_kbl/devicetree.cb | 2 +- src/mainboard/purism/librem_skl/devicetree.cb | 2 +- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 2 +- 53 files changed, 53 insertions(+), 53 deletions(-) diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 9151d7f1db..1338292e79 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb index a802ccabee..18109c8c87 100644 --- a/src/mainboard/aoostar/wtr_r1/devicetree.cb +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "s0ix_enable" = "true" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 59e297ca9f..d999973c3a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "PrimaryDisplay" = "Display_PEG" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 4c7aa16277..d7070fed48 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -22,7 +22,7 @@ chip soc/intel/skylake register "eist_enable" = "true" # DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index f0370ed1ac..89045163de 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -25,7 +25,7 @@ chip soc/intel/alderlake register "disable_c1_state_auto_demotion" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 18f02e6c99..3009f65703 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/alderlake register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b7b22d9444..6160ebf084 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/alderlake register "disable_package_c_state_demotion" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index 481bd2ef7f..6bd659dbce 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/alderlake register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 30e83092d8..65d3518b7b 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -32,7 +32,7 @@ chip soc/intel/alderlake register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 5dae5f38e9..4e21cde4ef 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -23,7 +23,7 @@ chip soc/intel/alderlake register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 5374666652..cdc777b0b0 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -23,7 +23,7 @@ chip soc/intel/alderlake register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "10" # TCC of 90 diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index f7ff7761a9..d792bc94a2 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -5,7 +5,7 @@ chip soc/intel/alderlake register "s0ix_enable" = "true" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "tcc_offset" = "5" # TCC of 100 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cc2b66d6d9..2b55e7c9eb 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@ chip soc/intel/jasperlake register "DdiPortCDdc" = "1" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Power limit config register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 561685ff73..971d886e29 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -40,7 +40,7 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 25, .tdp_pl2_override = 51, diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 5c9ce5d7a7..9c1cc44c45 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -184,7 +184,7 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 1eda1ab454..ed83f861de 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -53,7 +53,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4d3d517f78..7ae525564e 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8c33f0239b..0b4558b73e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ chip soc/intel/cannonlake # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 138499c884..671150d656 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -55,7 +55,7 @@ chip soc/intel/apollolake register "lpss_s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 0e1d21051f..5f81bec705 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 5180bd9619..51ba1998f2 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -19,7 +19,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 4a69cb3aca..c93cc4b883 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index f6116effa1..1187636287 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 15732388e8..289cc7231a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 5a12bdc62e..7869dc5f32 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 1274b787d4..f9edf263d5 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 08880cb308..2eee315e5b 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ chip soc/intel/cannonlake # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 8b42a1cb5d..5eee33e790 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -46,7 +46,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 0c1f1222c9..ecfd522560 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -46,7 +46,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 41e6669079..5385aaaccf 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -46,7 +46,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index abab1687c0..f27d26a5e4 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -43,7 +43,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 81cbef5884..e755776aae 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -46,7 +46,7 @@ chip soc/intel/apollolake register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 19eb34e21f..901d408348 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -45,7 +45,7 @@ chip soc/intel/meteorlake register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 2523fb9be2..b973cefbf1 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ chip soc/intel/meteorlake register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 04b7cf69de..1048acb081 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -45,7 +45,7 @@ chip soc/intel/meteorlake register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 4aba20b19d..6df6c7368b 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ chip soc/intel/meteorlake register "pch_pm_energy_report_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 7eec7a8724..d2458441c9 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e01e6601f9..569abe5394 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -31,7 +31,7 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index aa5c08f14c..ac55ac07a6 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -198,7 +198,7 @@ chip soc/intel/tigerlake register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Enable External Bypass register "external_bypass" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 74ceca1fa5..031b2f059b 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -133,7 +133,7 @@ chip soc/intel/alderlake register "tcss_aux_ori" = "0" register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index c3b398d6c3..1eff9459d3 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -17,7 +17,7 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # eMMC HS400 register "emmc_enable_hs400_mode" = "true" diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 7a46e1099a..dc0ae8a94f 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ chip soc/intel/apollolake register "emmc_tx_cmd_cntl" = "0x1305" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # PL1 override: 7.5W setting gives a run-time 6W actual # Set RAPL PL2 to 15W. diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 4bcdddd4ed..56c7bd6a0b 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -116,7 +116,7 @@ chip soc/intel/jasperlake }" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index dc44770762..473e586a1c 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "IoBufferOwnership" = "0" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index e5480e2ba9..1a565e50f7 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index d4f2ea3fcc..6d14b5819b 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -115,7 +115,7 @@ chip soc/intel/meteorlake register "pch_hda_idisp_codec_enable" = "1" # DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true" device domain 0 on device ref igpu on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 69ec54636c..70adca6492 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -71,7 +71,7 @@ chip soc/intel/tigerlake register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fbb8418ff9..d1deea3416 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -78,7 +78,7 @@ chip soc/intel/tigerlake register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" # Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 953c8191f4..3291e1d2e1 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -3,7 +3,7 @@ chip soc/intel/apollolake register "enable_vtd" = "1" - register "dptf_enable" = "1" + register "dptf_enable" = "true" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f129128d8a..3b440a0b4c 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d2d55dec92..fd20b1530c 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/skylake register "eist_enable" = "true" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" register "tcc_offset" = "5" # TCC of 95C diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 610c737c70..18ffb1b52d 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -35,7 +35,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 426a2899c7..13ca6e7782 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/skylake register "gpe0_dw2" = "GPP_E" # Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false" # FSP Configuration register "DspEnable" = "0"