From 65dc0bdd7eb98ba0fab90dc6a04f9574ec07b999 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 Oct 2025 22:43:27 +0530 Subject: [PATCH] mainboard/fatcat/lapis: Override PMC GPE configuration Set the GPE0 registers (DW0, DW1, and DW2) to configure General Purpose Events (GPEs) for the Lapis variant. This configures GPP_VGPIO, GPP_F, and GPP_E as the Tier-1 PMC GPIO groups. This patch ensures the variant can override the default baseboard (fatcat) GPE settings, which may not align with the variant's (aka lapis) hardware. BUG=b:414614106 TEST=Able to override PMC GPEs as per google/lapis configuration. Change-Id: Icd191d5265619ebfbf7f8dabb39a91a6517dfbd8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/89835 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N Reviewed-by: Paul Menzel Reviewed-by: hualin wei --- src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb index d9ce5bc352..c686dd4da2 100644 --- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb @@ -37,6 +37,10 @@ fw_config end chip soc/intel/pantherlake + # GPE configuration override + register "pmc_gpe0_dw0" = "GPP_VGPIO" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" register "power_limits_config[PTL_CORE_1]" = "{ .tdp_pl1_override = 15,