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rockchip: rk3288: correct ddr 300MHz clock setting

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CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz
setting can't meet this request, so modify it

BRANCH=None
BUG=None
TEST=Set ddr frequency to 300MHz and boot from mickey

Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/282445
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I885704542293ed55e429a0b4b30135af7978990f
Reviewed-on: https://chromium-review.googlesource.com/284095
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
huang lin 2015-06-30 10:01:14 +08:00 • committed by ChromeOS Commit Bot
commit 6495b27e70
1 changed files with 1 additions and 1 deletions
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2
src/soc/rockchip/rk3288/clock.c
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@ -376,7 +376,7 @@ void rkclk_configure_ddr(unsigned int hz)
switch (hz) {
case 300*MHz:
dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1};
dpll_cfg = (struct pll_div){.nf = 50, .nr = 2, .no = 2};
break;
case 533*MHz: /* actually 533.3P MHz */
dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2};