From 6495b27e70d3e34601c2786029eb48dd082cd224 Mon Sep 17 00:00:00 2001 From: huang lin Date: Tue, 30 Jun 2015 10:01:14 +0800 Subject: [PATCH] rockchip: rk3288: correct ddr 300MHz clock setting CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz setting can't meet this request, so modify it BRANCH=None BUG=None TEST=Set ddr frequency to 300MHz and boot from mickey Signed-off-by: huang lin Reviewed-on: https://chromium-review.googlesource.com/282445 Reviewed-by: David Hendricks Reviewed-by: Julius Werner Change-Id: I885704542293ed55e429a0b4b30135af7978990f Reviewed-on: https://chromium-review.googlesource.com/284095 Tested-by: David Hendricks Commit-Queue: David Hendricks --- src/soc/rockchip/rk3288/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 45a9ea3391..6ec3389576 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -376,7 +376,7 @@ void rkclk_configure_ddr(unsigned int hz) switch (hz) { case 300*MHz: - dpll_cfg = (struct pll_div){.nf = 25, .nr = 2, .no = 1}; + dpll_cfg = (struct pll_div){.nf = 50, .nr = 2, .no = 2}; break; case 533*MHz: /* actually 533.3P MHz */ dpll_cfg = (struct pll_div){.nf = 400, .nr = 9, .no = 2};