From 639def1d84fae566a46be906fc12a3c3ee56b33d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 21 Dec 2024 18:18:17 +0000 Subject: [PATCH] mb/google/fatcat/var/fatcat: Enable FPS Lists of changes: - GPIO programmimg when FW_CONFIG bit 17 is set FPMCU_PWREN -> GPP_E19 -> OUTPUT SOC_INT_L -> GPP_D1 -> INPUT FPMCU_FW_UPDATE -> GPP_E20 -> NF1 FPS_RST_N -> GPP_C15 -> OUTPUT GPP_F16_GSPI0A_CLK -> GPP_F16 -> SPI CLK -> NF8 GPP_F15_GSPI0A_MISO -> GPP_F15 -> SPI MISO -> NF8 GPP_F14_GPSI0A_MOSI -> GPP_F14 -> SPI MOSI -> NF8 GPP_F18_GSPI0A_CS0 -> GPP_F18 -> SPI CS -> NF8 - GPIO programmimg when FW_CONFIG bit 17 is not set GPP_E19 -> NC MOD_TCSS1_TYP_A_VBUS_EN -> GPP_D1 -> OUTPUT GPP_E20 -> NC GPP_C15 -> NC GPP_F16 -> NC GPP_F15 -> NC GPP_F14 -> NC GPP_F18 -> NC - ACPI Entry - Keep ISH (0x12.0) enable for GSPI0A to be operational - Keep GSPI0/1 disable and GSPI0A enable (PCI) BUG=b:377595986 TEST=TBD Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85687 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- .../google/fatcat/variants/fatcat/fw_config.c | 45 +++++++++++++++++++ .../google/fatcat/variants/fatcat/gpio.c | 16 ------- .../fatcat/variants/fatcat/overridetree.cb | 25 +++++++++++ 3 files changed, 70 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index b061f7cb9c..728d0f9171 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -474,6 +474,42 @@ static const struct pad_config ish_enable_pads[] = { PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8), }; +static const struct pad_config fp_disable_pads[] = { + PAD_NC(GPP_C15, NONE), + /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F18, NONE), +}; + +static const struct pad_config fp_enable_pads[] = { + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), + /* GPP_D01: FPS_SOC_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT), + /* GPP_E19: FPMCU_PWREN */ + PAD_CFG_GPO(GPP_E19, 1, DEEP), + /* GPP_E20: FPMCU_FW_UPDATE */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_F14: GPSI0A_MOSI */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), + /* GPP_F15: GSPI0A_MISO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), + /* GPP_F16: GPSI0A_CLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), + /* GPP_F18: GSPI0A_CS0 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), +}; + +static const struct pad_config pre_mem_fp_enable_pads[] = { + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), +}; + void fw_config_configure_pre_mem_gpio(void) { if (!fw_config_is_provisioned()) { @@ -517,6 +553,10 @@ void fw_config_configure_pre_mem_gpio(void) */ if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads); + + if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) + GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads); + } void fw_config_gpio_padbased_override(struct pad_config *padbased_table) @@ -607,4 +647,9 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) /* NOTE: disable PEG (x8 slot) and x4 slot wake for now */ GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads); + + if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) + GPIO_CONFIGURE_PADS(fp_enable_pads); + else + GPIO_CONFIGURE_PADS(fp_disable_pads); } diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 47a5c3a14f..a5a1be13e5 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -130,8 +130,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* GPP_C14: CLKREQ5_X1_GEN4_M2_WWAN_N */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), - /* GPP_C15: CRD1_CLK_EN */ - PAD_CFG_GPO(GPP_C15, 1, PLTRST), /* GPP_C16: TBT_LSX0_TXD */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GPP_C17: TBT_LSX0_RXD */ @@ -151,8 +149,6 @@ static const struct pad_config gpio_table[] = { /* GPP_D00: IMGCLKOUT_1 */ PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), - /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ - PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPP_D02: Not used */ PAD_NC(GPP_D02, NONE), /* GPP_D03: M.2_WWAN_PERST_GPIO_N */ @@ -234,10 +230,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), - /* GPP_E19: PEG_SLOT_DGPU_SEL_N */ - PAD_CFG_GPO(GPP_E19, 1, PLTRST), - /* GPP_E20: PEG_SLOT_DGPU_PWR_OK */ - PAD_CFG_GPI(GPP_E20, NONE, PLTRST), /* GPP_E21: I2C_PMC_PD_INT_N */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22: THC0_SPI1_DSYNC */ @@ -277,16 +269,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), - /* GPP_F14: Not used */ - PAD_NC(GPP_F14, NONE), - /* GPP_F15: Not used */ - PAD_NC(GPP_F15, NONE), - /* GPP_F16: Not used */ - PAD_NC(GPP_F16, NONE), /* GPP_F17: Not used */ PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH), - /* GPP_F18: TCH_PAD_INT_N */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPP_F19: GPP_PRIVACY_LED_CAM2 */ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */ diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index ca2ebb03b9..60fb95f07e 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -107,6 +107,12 @@ chip soc/intel/pantherlake [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0A] = PchSerialIoPci, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -357,12 +363,31 @@ chip soc/intel/pantherlake device ref ish on probe ISH ISH_ENABLE + probe FP FP_PRESENT chip drivers/intel/ish register "add_acpi_dma_property" = "true" device generic 0 on end end end + device ref gspi0a on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)" + register "wake" = "GPE0_DW1_01" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" + register "enable_delay_ms" = "3" + device spi 0 on + probe FP FP_PRESENT + end + end # FPMCU + end + device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on