mb/siemens/mc_ehl{1..5}: Unify devicetrees SerialIoI2cPadsTermination

Unify the I2C pad termination on all mc_ehl boards for better code
readability and continuity in the devicetrees. This patch does not
change the actual I2C pad termination configuration.

All the mc_ehl boards use external resistors for I2C termination.
Therefore, there is no need for internal termination at all. If the FSP
parameter 'SerialIoI2cPadsTermination' is omitted from the device tree,
the generic GPIO settings can define termination. If
'SerialIoI2cPadsTermination' is specified for an inactive I2C
controller, those settings are ignored.

This patch consistently adds 'SerialIoI2cPadsTermination' to the device
tree for all active mc_ehl boards, and removes it for controllers that
are switched off.
This topic came up in review for commit 864e3ca661
("mb/siemens/mc_ehl6: Adjust I2C setup").

TEST=Build and boot to OS on mc_ehl1/2/4 and compare register contents
of PAD_CFG_DW0/1 registers for all 8 I2C controllers before and after
the patch to ensure no change in I2C pad termination.

Change-Id: Iba75778893e0b6a7acb68535d0407dc1fc43d2ca
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb

@@ -95,14 +95,8 @@ chip soc/intel/elkhartlake
 	}"
 
 	register "SerialIoI2cPadsTermination" = "{
-		[PchSerialIoIndexI2C0] = 1,
 		[PchSerialIoIndexI2C1] = 1,
-		[PchSerialIoIndexI2C2] = 1,
-		[PchSerialIoIndexI2C3] = 1,
 		[PchSerialIoIndexI2C4] = 1,
-		[PchSerialIoIndexI2C5] = 1,
-		[PchSerialIoIndexI2C6] = 1,
-		[PchSerialIoIndexI2C7] = 1,
 	}"
 
 	register "SerialIoUartMode" = "{

src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb

@@ -82,6 +82,15 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C0] = 1,
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C3] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C5] = 1,
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,

src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb

@@ -84,6 +84,15 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C0] = 1,
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C3] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C5] = 1,
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,

src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb

@@ -102,14 +102,8 @@ chip soc/intel/elkhartlake
 	}"
 
 	register "SerialIoI2cPadsTermination" = "{
-		[PchSerialIoIndexI2C0] = 1,
 		[PchSerialIoIndexI2C1] = 1,
-		[PchSerialIoIndexI2C2] = 1,
-		[PchSerialIoIndexI2C3] = 1,
 		[PchSerialIoIndexI2C4] = 1,
-		[PchSerialIoIndexI2C5] = 1,
-		[PchSerialIoIndexI2C6] = 1,
-		[PchSerialIoIndexI2C7] = 1,
 	}"
 
 	register "SerialIoUartMode" = "{

src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb

@@ -82,6 +82,15 @@ chip soc/intel/elkhartlake
 		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
 	}"
 
+	register "SerialIoI2cPadsTermination" = "{
+		[PchSerialIoIndexI2C0] = 1,
+		[PchSerialIoIndexI2C1] = 1,
+		[PchSerialIoIndexI2C2] = 1,
+		[PchSerialIoIndexI2C3] = 1,
+		[PchSerialIoIndexI2C4] = 1,
+		[PchSerialIoIndexI2C5] = 1,
+	}"
+
 	register "SerialIoUartMode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoPci,