From 61ce86ea3edfbae4c3470778c6d43e4fa37a07d1 Mon Sep 17 00:00:00 2001 From: Uwe Poeche Date: Tue, 3 Feb 2026 15:31:25 +0100 Subject: [PATCH] mb/siemens/mc_ehl6: Reduce clock rate for I2C1 Signal integrity measurement on I2C1 bus showed not optimal rise time. Therefore the clock frequency is reduced from 400kHz to 100kHz to reach optimal signal integrity also during coreboot runtime. TEST=Signal integrity measurement during coreboot runtime. Change-Id: I9721ede7aa645b2ca46f377bbe557f78c36581f6 Signed-off-by: Uwe Poeche Reviewed-on: https://review.coreboot.org/c/coreboot/+/91079 Reviewed-by: Mario Scheithauer Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb index 5180770908..f47fde0cab 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb @@ -111,6 +111,12 @@ chip soc/intel/elkhartlake [PchSerialIoIndexI2C6] = 1, }" + register "common_soc_config" = "{ + .i2c[1] = { + .speed = I2C_SPEED_STANDARD, + }, + }" + register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoPci,