diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index a097ea7142..90091d06f6 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -85,17 +85,17 @@ chip soc/intel/pantherlake
 	register "cep_enable[VR_DOMAIN_GT]" = "true"
 	register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
 	register "cep_enable[VR_DOMAIN_SA]" = "true"
-	register "fast_vmode_i_trip[PTL_U_1_CORE]" = "{
+	register "fast_vmode_i_trip[PTL_CORE_1]" = "{
 		[VR_DOMAIN_IA] = 63 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
-	register "fast_vmode_i_trip[PTL_U_2_CORE]" = "{
+	register "fast_vmode_i_trip[PTL_CORE_2]" = "{
 		[VR_DOMAIN_IA] = 63 * 4,
 		[VR_DOMAIN_GT] = 38 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
 	}"
-	register "fast_vmode_i_trip[PTL_H_1_CORE]" = "{
+	register "fast_vmode_i_trip[PTL_CORE_3]" = "{
 		[VR_DOMAIN_IA] = 75 * 4,
 		[VR_DOMAIN_GT] = 75 * 4,
 		[VR_DOMAIN_SA] = 38 * 4
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
index f83d9bdd48..224dda7443 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
@@ -25,67 +25,67 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
+		.power_limits_index = PTL_CORE_3,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_1_CORE,
+		.power_limits_index = PTL_CORE_3,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_5,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_6,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_7,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_H_ID_8,
 		.cpu_tdp = TDP_25W,
-		.power_limits_index = PTL_H_2_CORE,
+		.power_limits_index = PTL_CORE_4,
 		COMMON_PTL_H_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_1,
 		.cpu_tdp = TDP_15W,
-		.power_limits_index = PTL_U_1_CORE,
+		.power_limits_index = PTL_CORE_1,
 		COMMON_PTL_U_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_2,
 		.cpu_tdp = TDP_15W,
-		.power_limits_index = PTL_U_2_CORE,
+		.power_limits_index = PTL_CORE_2,
 		COMMON_PTL_U_POWER_LIMITS
 	},
 	{
 		.mch_id = PCI_DID_INTEL_PTL_U_ID_3,
 		.cpu_tdp = TDP_15W,
-		.power_limits_index = PTL_U_2_CORE,
+		.power_limits_index = PTL_CORE_2,
 		COMMON_PTL_U_POWER_LIMITS
 	},
 };
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index d2bbc80767..7e8c97268c 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -43,17 +43,17 @@ end
 
 chip soc/intel/pantherlake
 
-	register "power_limits_config[PTL_U_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
index b06207f9ed..c1ed2a9400 100644
--- a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -23,13 +23,13 @@ chip soc/intel/pantherlake
 	# The initial version temporarily uses the PTL-H,
 	# but the thermal design is based on the PTL-U.
 	# Apply PTL-U's thermal settings here to avoid thermal issues.
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
index 3231689c82..cf2ad628fa 100644
--- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb
@@ -1,16 +1,16 @@
 chip soc/intel/pantherlake
 
-	register "power_limits_config[PTL_U_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 25,
 	}"
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index b06207f9ed..c1ed2a9400 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -23,13 +23,13 @@ chip soc/intel/pantherlake
 	# The initial version temporarily uses the PTL-H,
 	# but the thermal design is based on the PTL-U.
 	# Apply PTL-U's thermal settings here to avoid thermal issues.
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
 	}"
 
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 152,
diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c
index 871d19306f..540358238d 100644
--- a/src/soc/intel/pantherlake/bootblock/report_platform.c
+++ b/src/soc/intel/pantherlake/bootblock/report_platform.c
@@ -54,9 +54,9 @@ static struct {
 	const char *name;
 } pch_table[] = {
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_0, "Pantherlake SOC-UH" },
-	{ PCI_DID_INTEL_PTL_U_H_ESPI_1, "Pantherlake SOC-UH SuperSKU" },
-	{ PCI_DID_INTEL_PTL_U_H_ESPI_2, "Pantherlake SOC-UH Premium" },
-	{ PCI_DID_INTEL_PTL_U_H_ESPI_3, "Pantherlake SOC-UH Base" },
+	{ PCI_DID_INTEL_PTL_U_H_ESPI_1, "Pantherlake SOC-UH" },
+	{ PCI_DID_INTEL_PTL_U_H_ESPI_2, "Pantherlake SOC-UH" },
+	{ PCI_DID_INTEL_PTL_U_H_ESPI_3, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_4, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_5, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_6, "Pantherlake SOC-UH" },
@@ -86,9 +86,9 @@ static struct {
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_30, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_U_H_ESPI_31, "Pantherlake SOC-UH" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_0, "Pantherlake SOC-H" },
-	{ PCI_DID_INTEL_PTL_H_ESPI_1, "Pantherlake SOC-H SuperSKU" },
-	{ PCI_DID_INTEL_PTL_H_ESPI_2, "Pantherlake SOC-H Premium" },
-	{ PCI_DID_INTEL_PTL_H_ESPI_3, "Pantherlake SOC-H Base" },
+	{ PCI_DID_INTEL_PTL_H_ESPI_1, "Pantherlake SOC-H" },
+	{ PCI_DID_INTEL_PTL_H_ESPI_2, "Pantherlake SOC-H" },
+	{ PCI_DID_INTEL_PTL_H_ESPI_3, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_4, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_5, "Pantherlake SOC-H" },
 	{ PCI_DID_INTEL_PTL_H_ESPI_6, "Pantherlake SOC-H" },
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index c837ec6da9..cb37155adb 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -53,11 +53,11 @@ enum soc_intel_pantherlake_sagv_gears {
 };
 
 enum soc_intel_pantherlake_power_limits {
-	PTL_U_1_CORE,
-	PTL_U_2_CORE,
-	PTL_H_1_CORE,
-	PTL_H_2_CORE,
-	PTL_H_3_CORE,
+	PTL_CORE_1,
+	PTL_CORE_2,
+	PTL_CORE_3,
+	PTL_CORE_4,
+	PTL_CORE_5,
 	WCL_CORE,
 	PTL_POWER_LIMITS_COUNT,
 };
@@ -70,11 +70,11 @@ enum soc_intel_pantherlake_cpu_tdps {
 };
 
 enum soc_intel_pantherlake_sku {
-	PTL_H404_SKU,
-	PTL_H12XE_SKU,
-	PTL_H484_SKU,
-	PTL_H4XE_SKU,
-	PTL_H204_SKU,
+	PTL_SKU_1,
+	PTL_SKU_2,
+	PTL_SKU_3,
+	PTL_SKU_4,
+	PTL_SKU_5,
 	WCL_SKU_1,
 	WCL_SKU_2,
 	WCL_SKU_3,
@@ -90,20 +90,20 @@ static const struct soc_intel_pantherlake_power_map {
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
 	enum soc_intel_pantherlake_sku sku;
 } cpuid_to_ptl[] = {
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_25W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_25W, PTL_H204_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_15W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_25W, PTL_H404_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
-	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5 },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_15W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_25W, PTL_SKU_1 },
+	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3 },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
+	{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
+	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
 	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
 	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
 	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb
index e7cac8dd64..3ab98a260c 100644
--- a/src/soc/intel/pantherlake/chipset_ptl.cb
+++ b/src/soc/intel/pantherlake/chipset_ptl.cb
@@ -2,48 +2,44 @@ chip soc/intel/pantherlake
 
 	device cpu_cluster 0 on end
 
-	# H404
-	register "power_limits_config[PTL_U_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 55,
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
-	register "thermal_design_current[PTL_H404_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_1]" = "{
 		[VR_DOMAIN_IA] = 34 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 
-	# H204
-	register "power_limits_config[PTL_U_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_2]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 45,
 		.tdp_pl4 = 105,
 		.tdp_pl4_fastvmode = 95,
 	}"
-	register "thermal_design_current[PTL_H204_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_5]" = "{
 		[VR_DOMAIN_IA] = 23 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 
-	# H12Xe and H484
-	register "power_limits_config[PTL_H_1_CORE]" = "{
+	register "power_limits_config[PTL_CORE_3]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 64,
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
 	}"
-	register "thermal_design_current[PTL_H12XE_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_2]" = "{
 		[VR_DOMAIN_IA] = 39 * 8,
 		[VR_DOMAIN_GT] = 44 * 8
 	}"
-	register "thermal_design_current[PTL_H484_SKU]" = "{
+	register "thermal_design_current[PTL_SKU_3]" = "{
 		[VR_DOMAIN_IA] = 39 * 8,
 		[VR_DOMAIN_GT] = 23 * 8
 	}"
 
-	# H4XE
-	register "power_limits_config[PTL_H_2_CORE]" = "{
+	register "power_limits_config[PTL_CORE_4]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 64,
 		.tdp_pl4 = 154,