From 542dd2e4e64c6e4e1a7e32f3dd2b3d688f1de4bf Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Wed, 2 Oct 2024 12:12:00 +0100 Subject: [PATCH] soc/intel/alderlake: Fix PEG0 IRQ routing PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes: pcieport 0000:00:06.0: can't derive routing for PCI INT D pcieport 0000:00:06.0: PCI INT D: not connected PEG1 should also be PCI_INT_B. Tested on `starbook_adl` with Ubuntu 24.04 by running SSD benchmark with GNOME disks and suspend. Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/fsp_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 6b89bb2819..79fa893c72 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -98,8 +98,8 @@ static const struct slot_irq_constraints irq_constraints[] = { { .slot = SA_DEV_SLOT_CPU_6, .fns = { - FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), - FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_D, PIRQ_A), + FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_B, PIRQ_C), }, }, {