From 534fceb36a203c10a1cd65d9461768e6fb4fef5b Mon Sep 17 00:00:00 2001 From: Kilian Krause Date: Mon, 3 Nov 2025 17:38:22 +0100 Subject: [PATCH] mb/siemens/mc_rpl1: Set PCI bridge function for NC_FPGA Update EARLY_PCI_BRIDGE_FUNCTION from 0x0 to 0x2 for NC FPGA POST code communication. This matches the PCI bridge function where the NC FPGA is connected on this hardware. TEST=Built and booted on mc_rpl1. Verified that POST codes display correctly on the 7-segment display. Change-Id: I52c463036091ac42c6db415d1d3e582e561aff67 Signed-off-by: Kilian Krause Reviewed-on: https://review.coreboot.org/c/coreboot/+/89882 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig index 858cb3fce8..9bf0138051 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig @@ -24,7 +24,7 @@ config EARLY_PCI_BRIDGE_DEVICE config EARLY_PCI_BRIDGE_FUNCTION hex depends on NC_FPGA_POST_CODE - default 0x0 + default 0x2 config EARLY_PCI_MMIO_BASE hex