From 5271ac7ac5acb21f286d01a436cabbcc6cf3da51 Mon Sep 17 00:00:00 2001 From: Swathi Tamilselvan Date: Mon, 13 Oct 2025 16:30:16 +0530 Subject: [PATCH] soc/qualcomm/x1p42100: Reserve DDR carveout region Reserve DDR region for HYP, QTEE SMMU buffers, Gunyah and ACDB. The carveout is located at: 0xFF800000 - ((n*5.5)+1+32+3), where n is the DRAM size. This region is protected by QTEE and must remain reserved to prevent access by other components. TEST=1. Create an image.serial.bin and ensure it boots on X1P42100. 2. Verified carveout region reservation via depthcharge serial log. Prior to reservation, the memory wipeout range was [0x000000f61f7920, 0x000000ff800000). After reserving the carveout, the range is reduced to [0x000000f61f7920, 0x000000f7c00000). ``` Wipe memory regions: [0x00000080000000, 0x00000080a00000) [0x000000815a0000, 0x00000081a00000) [0x00000081cf4000, 0x00000081e00000) [0x00000082800000, 0x00000085380000) [0x00000085f80000, 0x000000866c0000) [0x00000091380000, 0x000000c72c4000) [0x000000c7800000, 0x000000d8000000) [0x000000d9600000, 0x000000f1000000) [0x000000f61f7920, 0x000000f7c00000) [0x00000880000000, 0x00000c00000000) ``` Change-Id: I511452054dcf10f8a2254eafb2f127c05a3249e5 Signed-off-by: Swathi Tamilselvan Reviewed-on: https://review.coreboot.org/c/coreboot/+/89552 Reviewed-by: Paul Menzel Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- src/soc/qualcomm/x1p42100/memlayout.ld | 2 ++ src/soc/qualcomm/x1p42100/soc.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld index 9996889cfd..b93a1e4c80 100644 --- a/src/soc/qualcomm/x1p42100/memlayout.ld +++ b/src/soc/qualcomm/x1p42100/memlayout.ld @@ -23,6 +23,8 @@ * 0xFFE00000 +----------------------------------------------------------+ | | * | dram_llcc_lpi | | | * 0xFF800000 +----------------------------------------------------------+ | | + * | dram_acdb | | | + * +----------------------------------------------------------+ | | * | ... Usable memory ... | | | * 0xDF4C0000 +----------------------------------------------------------+ | | * | dram_ta | | | diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c index f76ba44e24..ffa3a0e7d9 100644 --- a/src/soc/qualcomm/x1p42100/soc.c +++ b/src/soc/qualcomm/x1p42100/soc.c @@ -14,6 +14,11 @@ static struct device_operations pci_domain_ops = { .enable = &qcom_setup_pcie_host, }; +static uint64_t calc_acdb_carveout_size(void) +{ + return ((((region_sz(ddr_region) / GiB) * 11) / 2 + 36) * MiB); +} + static void soc_read_resources(struct device *dev) { int index = 0; @@ -43,6 +48,10 @@ static void soc_read_resources(struct device *dev) reserved_ram_range(dev, index++, (uintptr_t)_dram_wlan, REGION_SIZE(dram_wlan)); reserved_ram_range(dev, index++, (uintptr_t)_dram_pil, REGION_SIZE(dram_pil)); reserved_ram_range(dev, index++, (uintptr_t)_dram_ta, REGION_SIZE(dram_ta)); + + /* ACDB carveout region located at 0xFF800000 - (n*5.5 +1+32+3) where n is size of DDR */ + reserved_ram_range(dev, index++, (uintptr_t)(_dram_llcc_lpi - calc_acdb_carveout_size()), + calc_acdb_carveout_size()); reserved_ram_range(dev, index++, (uintptr_t)_dram_llcc_lpi, REGION_SIZE(dram_llcc_lpi)); reserved_ram_range(dev, index++, (uintptr_t)_dram_smem, REGION_SIZE(dram_smem)); }