From 51473811fa477cca9ad9cbafdaad4fd4a2309234 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Fri, 28 Mar 2014 19:13:51 +0800 Subject: [PATCH] tegra124: fix the dangerous VPR write order Currently we put the VPR write code just right before the AVP is going to freeze. We have no idea does the write operation successful or not before halting the AVP. And the power_on_main_cpu should be the last step of that. So we make a fix to change the order. BUG=none BRANCH=none TEST=LP0 suspend stress test and check the VPR is correct; LP0 suspend stress test with video playback Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372 Signed-off-by: Joseph Lo Reviewed-on: https://chromium-review.googlesource.com/192029 Reviewed-by: Tom Warren Reviewed-by: Andrew Bresticker Commit-Queue: Tom Warren Tested-by: Tom Warren --- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index ed3c97d71e..f4bea9e50e 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -599,13 +599,13 @@ void lp0_resume(void) config_tsc(); - power_on_main_cpu(); - // Disable VPR. write32(0, mc_video_protect_size_mb_ptr); write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, mc_video_protect_reg_ctrl_ptr); + power_on_main_cpu(); + // Halt the AVP. while (1) write32(FLOW_MODE_STOP | EVENT_JTAG,