diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index 2bd3a26b71..48f4dc77ce 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -13,13 +13,15 @@
 
 SECTIONS
 {
-	/* MT8196 has 256KB SRAM. */
+	/* MT8196 has 256KB SRAM. Per HW design, on SoC reset via GPIO
+	 * AP_SYSRST_ODL (SYSRSTB), SRAM will be powered down. That means
+	 * SRAM data will be lost across SoC resets.
+	 */
 	SRAM_START(0x00100000)
 	/* Regions that need to stay in SRAM. */
 	TTB(0x00100000, 28K)
 	DMA_COHERENT(0x00107000, 4K)
 	STACK(0x00108000, 15K)
-	WATCHDOG_TOMBSTONE(0x0010bc00, 4)
 	EARLY_INIT(0x0010bc10, 128)
 	/* EMPTY(0x0010bc90, 29K - 144) */
 	/*
@@ -56,7 +58,8 @@ SECTIONS
 	#endif
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K)
 	PRERAM_CBFS_CACHE(0x020DA000, 48K)
-	PRERAM_CBMEM_CONSOLE(0x020E6000, 340K)
+	PRERAM_CBMEM_CONSOLE(0x020E6000, 339K)
+	WATCHDOG_TOMBSTONE(0x0213AC00, 4)
 	FSP_ROMSTAGE_INIT_CODE(0x02140000, 64K)
 	SRAM_L2C_END(0x02200000)