erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/mediatek/mt8196: Add I2C driver support

Browse source 
Add I2C controller driver.

TEST=build pass
BUG=317009620

Change-Id: I617ad8a43ce8b492b1a0e5dc06c1f0ffe7d92b5e
Signed-off-by: ot_hao.han@mediatek.corp-partner.google.com
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83927
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Hao Han 2024-03-04 15:39:37 +08:00 • committed by Felix Held
commit 50a3fd18f2
4 changed files with 303 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/soc/mediatek/mt8196/Makefile.mk
View file

@ -4,6 +4,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8196),y)
all-y += ../common/flash_controller.c
all-y += ../common/gpio.c ../common/gpio_op.c gpio.c
all-y += ../common/i2c.c i2c.c
all-$(CONFIG_SPI_FLASH) += spi.c
all-y += timer.c
all-y += ../common/uart.c

198
src/soc/mediatek/mt8196/i2c.c Normal file
View file

@ -0,0 +1,198 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is created based on MT8196 Functional Specification
* Chapter number: 13.5
*/
#include <assert.h>
#include <console/console.h>
#include <device/i2c_simple.h>
#include <device/mmio.h>
#include <soc/i2c.h>
#include <soc/gpio.h>
struct mtk_i2c mtk_i2c_bus_controller[] = {
[0] = {
.i2c_regs = (void *)(I2C0_BASE),
.i2c_dma_regs = (void *)(I2C0_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[1] = {
.i2c_regs = (void *)(I2C1_BASE),
.i2c_dma_regs = (void *)(I2C1_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[2] = {
.i2c_regs = (void *)(I2C2_BASE),
.i2c_dma_regs = (void *)(I2C2_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[3] = {
.i2c_regs = (void *)(I2C3_BASE),
.i2c_dma_regs = (void *)(I2C3_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[4] = {
.i2c_regs = (void *)(I2C4_BASE),
.i2c_dma_regs = (void *)(I2C4_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[5] = {
.i2c_regs = (void *)(I2C5_BASE),
.i2c_dma_regs = (void *)(I2C5_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[6] = {
.i2c_regs = (void *)(I2C6_BASE),
.i2c_dma_regs = (void *)(I2C6_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[7] = {
.i2c_regs = (void *)(I2C7_BASE),
.i2c_dma_regs = (void *)(I2C7_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[8] = {
.i2c_regs = (void *)(I2C8_BASE),
.i2c_dma_regs = (void *)(I2C8_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[9] = {
.i2c_regs = (void *)(I2C9_BASE),
.i2c_dma_regs = (void *)(I2C9_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[10] = {
.i2c_regs = (void *)(I2C10_BASE),
.i2c_dma_regs = (void *)(I2C10_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[11] = {
.i2c_regs = (void *)(I2C11_BASE),
.i2c_dma_regs = (void *)(I2C11_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[12] = {
.i2c_regs = (void *)(I2C12_BASE),
.i2c_dma_regs = (void *)(I2C12_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[13] = {
.i2c_regs = (void *)(I2C13_BASE),
.i2c_dma_regs = (void *)(I2C13_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
[14] = {
.i2c_regs = (void *)(I2C14_BASE),
.i2c_dma_regs = (void *)(I2C14_DMA_BASE),
.mt_i2c_flag = I2C_APDMA_ASYNC,
},
};
_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
"Wrong size of mtk_i2c_bus_controller");
struct pad_func {
gpio_t gpio;
u8 func;
};
#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func}
static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
[0] = {
PAD_FUNC(SDA0, SDA0),
PAD_FUNC(SCL0, SCL0),
},
[1] = {
PAD_FUNC(SDA1, SDA1),
PAD_FUNC(SCL1, SCL1),
},
[2] = {
PAD_FUNC(CAM_SDA2, SDA2),
PAD_FUNC(CAM_SCL2, SCL2),
},
[3] = {
PAD_FUNC(SDA3, SDA3),
PAD_FUNC(SCL3, SCL3),
},
[4] = {
PAD_FUNC(CAM_SDA4, SDA4),
PAD_FUNC(CAM_SCL4, SCL4),
},
[5] = {
PAD_FUNC(SDA5, SDA5),
PAD_FUNC(SCL5, SCL5),
},
[6] = {
PAD_FUNC(SDA6, SDA6),
PAD_FUNC(SCL6, SCL6),
},
[7] = {
PAD_FUNC(CAM_SDA7, SDA7),
PAD_FUNC(CAM_SCL7, SCL7),
},
[8] = {
PAD_FUNC(CAM_SDA8, SDA8),
PAD_FUNC(CAM_SCL8, SCL8),
},
[9] = {
PAD_FUNC(CAM_SDA9, SDA9),
PAD_FUNC(CAM_SCL9, SCL9),
},
[10] = {
PAD_FUNC(SDA10, SDA10),
PAD_FUNC(SCL10, SCL10),
},
[11] = {
PAD_FUNC(CAM_PDN3, SDA11),
PAD_FUNC(CAM_PDN2, SCL11),
},
[12] = {
PAD_FUNC(CAM_PDN5, SDA12),
PAD_FUNC(CAM_PDN4, SCL12),
},
[13] = {
PAD_FUNC(CAM_PDN7, SDA13),
PAD_FUNC(CAM_PDN6, SCL13),
},
[14] = {
PAD_FUNC(SCP_SDA3, SDA14),
PAD_FUNC(SCP_SCL3, SCL14),
},
};
static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
{
assert(bus < I2C_BUS_NUMBER);
const struct pad_func *ptr = i2c_funcs[bus];
for (size_t i = 0; i < 2; i++) {
gpio_set_mode(ptr[i].gpio, ptr[i].func);
gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
}
}
void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
{
mtk_i2c_speed_init(bus, speed);
mtk_i2c_set_gpio_pinmux(bus);
}
void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
{
printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
read32(&regs->ltiming),
read32(&regs->clock_div));
}
void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
{
write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
write32(&regs->timing, bus_ctrl->ac_timing.htiming);
write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming);
write32(&regs->hs, bus_ctrl->ac_timing.hs);
write32(&regs->ext_conf, bus_ctrl->ac_timing.ext);
}

32
src/soc/mediatek/mt8196/include/soc/addressmap.h
View file

@ -36,6 +36,7 @@ enum {
IOCFG_RM1_BASE = IO_PHYS + 0x02020000,
IOCFG_RM2_BASE = IO_PHYS + 0x02040000,
IOCFG_RB_BASE = IO_PHYS + 0x02060000,
I2C5_BASE = IO_PHYS + 0x020A0000,
IOCFG_BM1_BASE = IO_PHYS + 0x02820000,
IOCFG_BM2_BASE = IO_PHYS + 0x02840000,
IOCFG_BM3_BASE = IO_PHYS + 0x02860000,
@ -45,10 +46,20 @@ enum {
MIPITX0_BASE = IO_PHYS + 0x030b0000,
IOCFG_LB1_BASE = IO_PHYS + 0x030f0000,
IOCFG_LB2_BASE = IO_PHYS + 0x03110000,
I2C0_BASE = IO_PHYS + 0x03130000,
I2C3_BASE = IO_PHYS + 0x03150000,
I2C6_BASE = IO_PHYS + 0x03170000,
I2C10_BASE = IO_PHYS + 0x03190000,
EFUSEC_BASE = IO_PHYS + 0x03260000,
IOCFG_TM1_BASE = IO_PHYS + 0x03800000,
IOCFG_TM2_BASE = IO_PHYS + 0x03820000,
IOCFG_TM3_BASE = IO_PHYS + 0x03860000,
I2C1_BASE = IO_PHYS + 0x03930000,
I2C2_BASE = IO_PHYS + 0x039B0000,
I2C4_BASE = IO_PHYS + 0x03A30000,
I2C7_BASE = IO_PHYS + 0x03AB0000,
I2C8_BASE = IO_PHYS + 0x03B30000,
I2C9_BASE = IO_PHYS + 0x03BB0000,
THERM_CTRL_BASE = IO_PHYS + 0x04414000,
UART0_BASE = IO_PHYS + 0x06000000,
SPI0_BASE = IO_PHYS + 0x06110000,
@ -59,7 +70,26 @@ enum {
SPI5_BASE = IO_PHYS + 0x061B0000,
SPI6_BASE = IO_PHYS + 0x0619D000,
SPI7_BASE = IO_PHYS + 0x061F0000,
SFLASH_REG_BASE = IO_PHYS + 0x06340000,
I2C11_BASE = IO_PHYS + 0x06200000,
I2C12_BASE = IO_PHYS + 0x06240000,
I2C13_BASE = IO_PHYS + 0x06280000,
I2C14_BASE = IO_PHYS + 0x062C0000,
SFLASH_REG_BASE = IO_PHYS + 0x06340000,
I2C0_DMA_BASE = IO_PHYS + 0x06370000,
I2C1_DMA_BASE = IO_PHYS + 0x06380000,
I2C2_DMA_BASE = IO_PHYS + 0x06390000,
I2C3_DMA_BASE = IO_PHYS + 0x063C0000,
I2C4_DMA_BASE = IO_PHYS + 0x063D0000,
I2C5_DMA_BASE = IO_PHYS + 0x06400000,
I2C6_DMA_BASE = IO_PHYS + 0x06410000,
I2C7_DMA_BASE = IO_PHYS + 0x06420000,
I2C8_DMA_BASE = IO_PHYS + 0x06450000,
I2C9_DMA_BASE = IO_PHYS + 0x06480000,
I2C10_DMA_BASE = IO_PHYS + 0x064B0000,
I2C11_DMA_BASE = IO_PHYS + 0x064C0000,
I2C12_DMA_BASE = IO_PHYS + 0x064D0000,
I2C13_DMA_BASE = IO_PHYS + 0x064F0000,
I2C14_DMA_BASE = IO_PHYS + 0x06500000,
PERICFG_AO_BASE = IO_PHYS + 0x06640000,
SSUSB_IPPC_BASE = IO_PHYS + 0x06703E00,
SSUSB_SIF_BASE = IO_PHYS + 0x06730300,

73
src/soc/mediatek/mt8196/include/soc/i2c.h Normal file
View file

@ -0,0 +1,73 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is created based on MT8196 Functional Specification
* Chapter number: 13.5
*/
#ifndef __SOC_MEDIATEK_MT8196_I2C_H__
#define __SOC_MEDIATEK_MT8196_I2C_H__
#include <soc/i2c_common.h>
#include <soc/pll.h>
/* I2C Register */
struct mt_i2c_regs {
uint32_t data_port;
uint32_t reserved0[1];
uint32_t intr_mask;
uint32_t intr_stat;
uint32_t control;
uint32_t transfer_len;
uint32_t transac_len;
uint32_t delay_len;
uint32_t timing;
uint32_t start;
uint32_t ext_conf;
uint32_t ltiming;
uint32_t hs;
uint32_t io_config;
uint32_t fifo_addr_clr;
uint32_t reserved1[2];
uint32_t transfer_aux_len;
uint32_t clock_div;
uint32_t time_out;
uint32_t softreset;
uint32_t reserved2[16];
uint32_t slave_addr;
uint32_t reserved3[19];
uint32_t debug_stat;
uint32_t debug_ctrl;
uint32_t reserved4[2];
uint32_t fifo_stat;
uint32_t fifo_thresh;
};
/* I2C ID Number */
enum {
I2C0,
I2C1,
I2C2,
I2C3,
I2C4,
I2C5,
I2C6,
I2C7,
I2C8,
I2C9,
I2C10,
I2C11,
I2C12,
I2C13,
I2C14,
};
#define I2C_BUS_NUMBER 15
#define MAX_CLOCK_DIV 32
#define I2C_CLK_HZ 124800000
check_member(mt_i2c_regs, fifo_thresh, 0xf8);
void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
#endif /* __SOC_MEDIATEK_MT8196_I2C_H__ */